Hi all, Through a testbench (Verilog or VHDL), how do I read the values of signals of a sub module through a top module? This is required to match and assert if the program is working correctly. Please help. Thank you.
Best Regards,
One possibility could be to route the internal signal to an output pin.=20
Rgds Andr=E9
Signals defined in a VHDL package can be global in scope.
-Jeff
In Verilog it's even easier. You can specify any signal using the module hierarchy and "." as a separator like:
top.instance1.signame
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