Problem with interfacingT-VPACK with ALTERA QUIP5.0

Sep 05, 2005 4 Replies

Hi All,



I am having problem when interfacing T-VPACK

formatting link
with QUIP5.0.



I have a 'test4.vhd' file: --------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL;



entity test4 is port ( a : in std_logic_vector(4 downto 0); b : in std_logic_vector(4 downto 0); c : out std_logic_vector(4 downto 0)); end test4;



architecture test4_arch of test4 is begin



c

there is error in you vhdl code, in this line : out std_logic_vector(4 downto

0)); delete the samecoln(;).

verilog code below gives the same error:

module test5 (a, b, c);

input [4:0] a, b; output [4:0] c;

assign c = a & b;

endmodule

Error: Net #10 (c[0]) has no driver and will cause memory corruption.

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