I'd like to ask the following. My design has 3 different generic inputs according to which it multiply instantiates some entities and generates the appropriate bus widths, arithmetic modules etc. I'd like to do a bottom up area estimation and come up with functions of area for the three generics. Although I could simply write down the percentages of chip area taken by each entity as the generics change etc, it is a bit inconsistent as Xilinx gives me different percentages for LUTs, IOBs etc.
What I'd like to ask is if there is an established metric for area estimation, e.g thousands of gates and if there is direct translation between number of IOBs, LUTs etc and that metric. I'm dealng with a Virtex II FPGA. Thanks