Latest threads in Field-Programmable Gate Arrays

Tree Representation of Logic Circuits

Hello Everyone I am now trying to simulate gate level evolution in software. I was unsure about the formation of my chr...

1 21yrs

apsolar

1 21yrs apsolar

CPU benchmark for Xilinx PAR

Here's a benchmark for PAR (high effort level) running on two different CPUs. The design utilized about 40% of an XC2V4...

9 21yrs

pg8192

9 21yrs pg8192

P&R speed higher than synthesis

Hi, I seem to be getting a higher P&R speed (I put a constraint on the only clk I have in the design) than that I got f...

1 21yrs

cmwee_nospam

1 21yrs cmwee_nospam

FFT implementation in Xilinx's Spartan 3

Hi members, I am a student and completely new to FPGA. I am learning VHDL. My objective is to implement FFT in spartan-...

3 21yrs

biot.spm

3 21yrs biot.spm

Please Help:Modelsim-Altera License "Verilog Computer Based training course"

Hello, I bought this book "Verilog Computer-Based Training Course" CD-ROM and was trying to install Modelsim-Altera 5.5...

0 21yrs

junnuthula

0 21yrs junnuthula

Microblaze & Memory DMA operation

Hi, To get started with Microblaze, I'm attempting to do a simple filtering application on audio, real-time. Audio is C...

13 21yrs

r_fpga_dev

13 21yrs r_fpga_dev

ISE 7.1i & Linux / reg code question

Hi, I've read through the archives for notes and hints on installing ISE 7.1i for Linux. I got curl, portmap, motif, et...

9 21yrs

r_fpga_dev

9 21yrs r_fpga_dev

reducing the number of IOBS in a design

how can you reduce the number if IOBs a design uses during synthesis? thanks -- Geoffrey Wall Masters Student in Electr...

3 21yrs

wallge

3 21yrs wallge

modelsim simulation problem

I am trying to load a EDK design in modelsim for simulation.I can successfully compile the files but when I try to simu...

2 21yrs

nitesh.guinde

2 21yrs nitesh.guinde

Xilkernel problem

Hi there, I'm having problems trying to use Xilkernel on a XPS system designed to work on a Virtex-II Pro FPGA with Mic...

0 21yrs

adrian.mora

0 21yrs adrian.mora

xilinx ise / update schematics

have archived my project manually (without using ise) and restored it. now, ecs tells me to update every macro instance...

0 21yrs

yourmomishot

0 21yrs yourmomishot

place and route

Hi! Is there a way to write a placer and router for Xilinx FPGAs. Or the FPGA technology is closed at this level ??

7 21yrs

taileb.mehdi

7 21yrs taileb.mehdi

Fatal errror in ISE 6.3 i

Hello Guys, I am facing fatal error when i am synthesizing my RTL code. The same code gets synthesized in synplify but...

3 21yrs

stud_lang_jap

3 21yrs stud_lang_jap

SDRAM quality

I've got my design talking to some (Kingston) KVR133X64/1G SDRAM modules and running at only 66MHz, doing some simple t...

8 21yrs

jon

8 21yrs jon

several ucf files?

How to manage several ucf files when working with different projects on the same chip? i.e. top_pads.ucf, that is always...

1 21yrs

stephane

1 21yrs stephane

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