place and route

Hi!

I think it is possible to write a conceptional placer and router. A lot of the Xilinx FPGA-architectures (the principal components) are described in the appropriated documentations.

To develop a placer and router, that will be able to produce the configurationdata for a fpga will be very difficulty, because the structure and meaning of the configurationdata is not documented in all details.

greetings, Sven

You could write a placer using the "User Constraint File) or .ucf.

When I say a P&R soft I mean replace Xilinx P&R. For doing this I need to undestand what is contained in the binary files produced by Xilinx P&R ;) This job is really impossible ? If very difficult ... any start points ?

impossible ... no very difficult ... yes

i needed round about 3 month to understand approximate 70 percent of the configurationdata for the virtex-II pro architecture (i mean the real binary, which is stored in the configurationmemory of the fpga). the problem is the realy big complexity of the routing resources and so the programming of the switch-boxes. a start-point :) ?!? analyse the binarys from very simple designs, which use just few configureable resources (connections, LUTs, FFs, etc.) of an configureable element (clb, bram interconnect, etc.)

GaLaKtIkUs=99 wrote:

Why?

What do you hope to accomplish with this knowledge?

I am curious.

Aust> When I say a P&R soft I mean replace Xilinx P&R.

my aim is to develop a reconfiguration application thats able to reconfigure a fpga. i don't want to use more configuration files / bitstreams, which are stored in memory and loaded on demand.