Hi, I seem to be getting a higher P&R speed (I put a constraint on the only clk I have in the design) than that I got from synthesis. Sometimes by up to
10 MHz. Is that possible? I am using ISE 6.3 and targeting a Virtex 2
1000 -4.
Thank you Adrian
10 MHz. Is that possible? I am using ISE 6.3 and targeting a Virtex 2
1000 -4.