Latest threads in Field-Programmable Gate Arrays

vhdl state maching problem

following is a part of the state machine im trying to design. when start is set to '1' it goes to rw_1. when in that st...

6 21yrs

manusha

6 21yrs manusha

Xilinx XUP + Linux (firmware loading problem!)

Hi I have some more insights in the problem connecting a "xilinx xup virtex II pro" board with linux: I just installed...

0 21yrs

st

0 21yrs st

ALTERA quartus II 5.0sp1 web edition can't program MAXII: error code 84

Hi group, I am trying to download the design compiled with quartus II 5.0sp1 web edition into MAX II chip EPM1270T144C5...

2 21yrs

VAX9000

2 21yrs VAX9000

External dpram similar to blockram of Xilinx device

Hello. Now I'm using Xilinx virtex2 (xc2v6000). I use blockram as dpram with read/write port a and read only port b. Si...

1 21yrs

codejk

1 21yrs codejk

lwip sockets on spartan 3 microblaze? Any examples?

Hi I have wasted several weeks trying to get xilinx libxil to work, only to find that it doesnt work. I found that it d...

2 21yrs

pingboypulsar

2 21yrs pingboypulsar

altera new bee

Hi, I'd like to learn programming a micro chip. I've heard the Altera is popular. Which one should I specifically deal...

4 21yrs

zoharl3

4 21yrs zoharl3

Making timing assignment in Quartus

Hi, when fitting my design (120MHz clock from PLL) I get some timing violations reported. For example: Slack -2.115 ns...

0 21yrs

ALuPin

0 21yrs ALuPin

Altera_VHDL_support library into Modelsim?

To all, I had compiled my SOPC design with my master peripheral + sdram controller + my own slave peripheral (address g...

2 21yrs

pinod01

2 21yrs pinod01

question about creating RPM

Hi, I have question about creating RPM and need help from xilinx expert. >From the xilinx application note, I should be...

1 21yrs

shihhsin.hu

1 21yrs shihhsin.hu

Cyclone on a shared configuration bus

Hello, is it possible to configure a Cyclone device connected to a shared serial configuration bus using the nCE signal...

0 21yrs

wyderskiREMOVE

0 21yrs wyderskiREMOVE

Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments

Dear FPGA and VHDL Experts, I am new to FPGA and VHDL. I would like to learn VHDL and start experimenting FPGA. I belei...

5 21yrs

kv

5 21yrs kv

MAPLD 2005 Postings On-line

Hi, Almost all of the presentations from the 2005 MAPLD (Military and Aerospace Programmable Logic Device) Internationa...

1 21yrs

richard.b.katz

1 21yrs richard.b.katz

"Free" core and license

Hallo, I have used one core downloded from "opecores.org" into a project which will be a commercial microcotroller. Whi...

3 21yrs

marcotoschi

3 21yrs marcotoschi

jbits

Hi! Can somebody give me some advices about jbits. I want to use it in reconfigurable computing. What are its limits. I...

7 21yrs

taileb.mehdi

7 21yrs taileb.mehdi

Question on Metastability

Using a VirtexE part. I have two banks of registers. One is actually a 32-bit counter running real slow at 1KHz (1mS ti...

11 21yrs

See_my_website_for_email

11 21yrs See_my_website_for_email

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