Hi,
when fitting my design (120MHz clock from PLL) I get some timing violations reported.
For example:
Slack -2.115 ns Actual fmax 79.61MHz
From reg_starge: REG_STAGE_1 | l_ulpi_ack
To ... l_ulpi_ack_h1
From Clock pll_bank1: ...|clk0
Required Setup Relationship 4.166ns Required Longest P2P Time 4.246ns Actual Longerst P2P Time 6.361ns
To correct these timing violations I open the Assignment Editor and specify a timing assignment for these registered nodes:
From l_ulpi_ack
To l_ulpi_ack_h1 Assignment Name Setup Relationship Value 4 ns Enabled Yes
Is that assignment sufficient to avoid the timing violation above ? Or would be an assignment "Maximum Delay" more appropiate ? What is the recommended approach ?
Thank you for your help and opinion.
Rgds Andr=E9