Latest threads in Field-Programmable Gate Arrays

I need an Altera Excalib EPXA10 DDR Dev Board...anybody got one?

Although I know that modern development has long since bypassed the Excalibur for processor+FPGA design, it happens to...

0 20yrs

mikedamour

0 20yrs mikedamour

802.11g solution usable for FPGA design

Hi all! I need to make wireless device using 802.11g or something else. I check some chips but here is PCI or USB inter...

0 20yrs

crimaniak

0 20yrs crimaniak

ML403 dcm phase shift reference design... anyone has a copy ?

I'm trying to play with the OPB MCH DDR controller (multichannel ddr controller) on Microblaze platform, on S3. Unfortu...

0 20yrs

removethis_pasini.a

0 20yrs removethis_pasini.a

Linux USB XUP board

Hi After some have reported success with the ise 7.1.04i i tried to get the impact running. The installation was runnin...

2 20yrs

st

2 20yrs st

Power Management for Xilinx and Altera FPGAs

Was just told about this site at National Semiconductor. Great idea Means I no longer need to worry too much about my p...

1 20yrs

alan.hutton

1 20yrs alan.hutton

C-to-gates experiences

I stumbled across a presentation at MAPLD regarding various C-to-gates tools. The authors at U of F compared several to...

3 20yrs

scraven

3 20yrs scraven

Synchronizer Flip Flop / Metastability

To exchange flags (1 bit signals) between two unrelated clocks, a single synchronizer flip flop to clock that signal is...

14 20yrs

sheinzle

14 20yrs sheinzle

Need help in Flash simulation module.

I'm designing a flash controller, target is ATMEL AT49BV160C. It's a 16-megbit (1M x 16) 3-volt Only Flash Memory. Here...

1 20yrs

jerryjsy

1 20yrs jerryjsy

Announcement Free Symposium on the Future of Configurable Hardware

The International Symposium on the Future of Configurable Hardware Organised by: The ACES research network and the Gent...

0 20yrs

mchristi

0 20yrs mchristi

downlaoding bit files to Xilinx FPGA

Hi All I want to download bit file to the FPGA to program it w/out using any GUIs like the JTAG programmer. I need to w...

12 20yrs

thakkar.anuja

12 20yrs thakkar.anuja

Hints for efficient 32 bit multiplier

Hello everybody, I'm interested in the implementation of a 32x32 bit multiplier (unsigned values). The target FPGA is V...

4 20yrs

giovanniparodi79

4 20yrs giovanniparodi79

Xilinx PAR -- WARNING:Route - CLK Net may have excessive skew...

Greetings, I am implementing a design whose system clock is generated by an MGT (the TXOUTCLK pin), based on higher fre...

1 20yrs

entanglebit

1 20yrs entanglebit

Network-on-Chip Architectures

Hi, does anyone know where I could find on the internet resources about network architectures and switches w/ support f...

0 20yrs

nospam.eric

0 20yrs nospam.eric

USB communication using PCI Logicore

I have bought the PCI logicore from the xilinx inorder to communicate with the USB port of Xilinx Ml310 board. but i ha...

0 20yrs

venkiba81

0 20yrs venkiba81

opb ip master/slave...arbiter problems

Hello all, I want to create an IP master on the OPB. I am using Xilinx Virtex2 (xc2v2000), and Xilinx platform studio (...

1 20yrs

melbadri

1 20yrs melbadri

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