Field-Programmable Gate Arrays

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10G serial port with no FEC?

Hi, Recently I noticed that Xilinx FPGA has RocketPHY 10Gbps serial interfaces using 64B66B encoding. However, it seems...
1 comments posted 21yrs
posted by francisontheweb
1 comments posted 21yrs posted by francisontheweb

802.11g solution usable for FPGA design

Hi all! I need to make wireless device using 802.11g or something else. I check some chips but here is PCI or USB inter...
0 comments posted 21yrs
posted by crimaniak
0 comments posted 21yrs posted by crimaniak

Linux USB XUP board

Hi After some have reported success with the ise 7.1.04i i tried to get the impact running. The installation was runnin...
2 comments posted 21yrs
posted by st
2 comments posted 21yrs posted by st

Power Management for Xilinx and Altera FPGAs

Was just told about this site at National Semiconductor. Great idea Means I no longer need to worry too much about my p...
1 comments posted 21yrs
posted by alan.hutton
1 comments posted 21yrs posted by alan.hutton

C-to-gates experiences

I stumbled across a presentation at MAPLD regarding various C-to-gates tools. The authors at U of F compared several to...
3 comments posted 21yrs
posted by scraven
3 comments posted 21yrs posted by scraven

Synchronizer Flip Flop / Metastability

To exchange flags (1 bit signals) between two unrelated clocks, a single synchronizer flip flop to clock that signal is...
14 comments posted 21yrs
posted by sheinzle
14 comments posted 21yrs posted by sheinzle

Need help in Flash simulation module.

I'm designing a flash controller, target is ATMEL AT49BV160C. It's a 16-megbit (1M x 16) 3-volt Only Flash Memory. Here...
1 comments posted 21yrs
posted by jerryjsy
1 comments posted 21yrs posted by jerryjsy

downlaoding bit files to Xilinx FPGA

Hi All I want to download bit file to the FPGA to program it w/out using any GUIs like the JTAG programmer. I need to w...
12 comments posted 21yrs
posted by thakkar.anuja
12 comments posted 21yrs posted by thakkar.anuja

Hints for efficient 32 bit multiplier

Hello everybody, I'm interested in the implementation of a 32x32 bit multiplier (unsigned values). The target FPGA is V...
4 comments posted 21yrs
posted by giovanniparodi79
4 comments posted 21yrs posted by giovanniparodi79

Network-on-Chip Architectures

Hi, does anyone know where I could find on the internet resources about network architectures and switches w/ support f...
0 comments posted 21yrs
posted by nospam.eric
0 comments posted 21yrs posted by nospam.eric

USB communication using PCI Logicore

I have bought the PCI logicore from the xilinx inorder to communicate with the USB port of Xilinx Ml310 board. but i ha...
0 comments posted 21yrs
posted by venkiba81
0 comments posted 21yrs posted by venkiba81