Hi everyone,
Now that I've got the Xilinx Web-tools running reasonably well under Linux, I'm noticing that sch2vhld, which converts a schema-drawing into vhdl, is spending almost all of its time waiting. It's not using the CPU, disk or network at all. This happens both when called from the command line directly, or from within ISE. This causes sch2vhdl to take about 4 minutes to convert just one small schematic, on a 1.4GHz Centrino CPU. And my current design consists of 6 schematics... The other tools (xst, mapper etc.) actually use the CPU and work with a normal speed. Does anybody know how to encourage sch2vhdl to actually get on with the job at hand?
Regards, Paul Boven.