please someone let me know the effects of having "ibuf_lvcmos33" for each input , "obuf_lvcmos33" for each output and "bufg" in some entity declarations. In addition please let me know the effect of mappimg clk to clock in the following entity declaration.
entity test is port (clock : in std_logic )
end clock ;
architecture arch_test of test is
signal clk : std_logic ; clk
This technique avoids excessive wear on the 'c' and 'o' keys of your computer. It's important to keep these keys in pristine condition in case you need to email for coffee or cocoa. HTH, Syms.
These connect the device pins to the design. If you are using synthesis, these will be inferred where needed.
No effect for syntheses, other than possible confusion. An extra delta delay for simulation. I would just change the port name to clk.
-- Mike Treseler
there is an industry accepted method for creating abbreviated names.... First drop the vowels clock => clck
then use industry standard TLA's if applicable... clock => clk
the exception is a reduction that becomes ambiguous
clear as mud I hope
Simon
Name the clock signal the way you want. These are only symbolic names and only the way you use them will determine whether they are clocks signals or not (or sometimes a combination of both).
clk
The clk is sort of a standard style.
I do think it is a good idea on your top level to map the IO pin to the clk signal in case you want to change that pin or switch to another clock source. This will save you from having to replace all the clk signals if you want to move your clock source.
If you have testbeds, too, these will probably all be written with clk drivers, and so it is sometime a good idea to write your subordinate modules with clk and map it on the upper hierarchial modules with such an assignmnet that you suggest below.
Brad Smallridge
The ibuf and obufs tell the tools what sort of I/O structure is to be used. There's some detail on this in the device datasheets.
Perhaps there's a language barrier here, but I have no idea what you're asking. I suspect that Symon feels the same way.
-a
what im asking is, we have "clock", which is an input to the entity and a signal called "clk" declared in the entity. The input "clock" is mapped to the signal "clk". In all other places only "clk" is used, but "clock" is never used. What is the difference of doing this from just using "clock" everywhere and eliminating "clk" altogether?
CMOS
I'd ask the question the other way round: why not call the input port 'clk'?
Nicolas
or why not go to the extreme and give it a meaningful name? like clk_100MHz
Sim> > what im asking is, we have "clock", which is an input to the entity and
you can have any name for clk and clock. what im asking is a technical question and not on naming standards of VHDL. Put it another way, my problem is, why do we need to map the input to a signal declared in the declaration and use that signal , rather than just using input. will it result in a different circuit being synthezised?
CMOS
We don't.
Input port IDs can be used directly anywhere in the architecture on the right side of an assignment.
my_var := my_inport;
Same for output port IDs used on the left side of a signal assignment:
my_outport
You can, and should, use the port signal "clock" instead of using assigned signal "clk."
There IS a restriction that applies to using _output_ ports within an entity's architecture. You can only assign to that signal; you cannot use it on the right-hand side of an assignment statement. So it's common to see:
entity foo (a : in std_logic; b : out std_logic); end entity foo;
architecture bar of foo is signal bletch : std_logic; begin bletch
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