Inferring design elements in ISE tool

I'm not sure what your professor is getting at.

Is he implying that you should always instantiate everything, even primitives such as AND gates? If so, then there's little point in using an HDL.

I suppose, though, that in a logic design course, it's vital that you learn the basics, so rather than coding a counter as count Second thing while making these design elements (like counter) with

Here's where inference helps you. The synthesis tool recognizes certain structures and knows about the specifics of the chip architecture and how to map those structures to the chip efficiently. I'll bet that in your case, your flops-and-gates implementation of a counter doesn't take advantage of an FPGA's special carry chain. And hopefully you're not coding a ripple counter!

-a

I got the answer. My counter not utilizing carry chain. and was using extra buffers , thats why delay was more.Now i think simple modules like counters,adders are better to infer then using them we can make a structural design.