Inferring design elements in ISE tool

I am using ISE tool for implementing my design.But i am facing a problem.In this tool it is written that some modules are supported to infer rather than inatantiate. My prof says to make design wholly structural . and using the modules available, just like we do in shematic. But since for some design elements , instatiating is not supported, i cant do it.I have to write a module code to infer that module.but according to prof this should not be the way.

Second thing while making these design elements (like counter) with flip flop and gates (for which instantiation is supported), its min clock period is large compared to the one which is inferred.Suggest me what can do here.

Third in case of inferring the element is mapped to some Macros and LUT.Can someone please explain me give some reference , what is phisically these are and to what hardware they are actually mapped.

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I'm not sure what your professor is getting at.

Is he implying that you should always instantiate everything, even primitives such as AND gates? If so, then there's little point in using an HDL.

I suppose, though, that in a logic design course, it's vital that you learn the basics, so rather than coding a counter as count Second thing while making these design elements (like counter) with

Here's where inference helps you. The synthesis tool recognizes certain structures and knows about the specifics of the chip architecture and how to map those structures to the chip efficiently. I'll bet that in your case, your flops-and-gates implementation of a counter doesn't take advantage of an FPGA's special carry chain. And hopefully you're not coding a ripple counter!


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Andy Peters

I got the answer. My counter not utilizing carry chain. and was using extra buffers , thats why delay was more.Now i think simple modules like counters,adders are better to infer then using them we can make a structural design.

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