Hi,
I've tried to assign pins in PACE for a verilog module like this (I selected a spartan 3 fg456 package):
module test_top(clkin, datain, dataout); input clkin; input datain; output dataout;
always @ (posedge clkin) dataout
Hi,
I've tried to assign pins in PACE for a verilog module like this (I selected a spartan 3 fg456 package):
module test_top(clkin, datain, dataout); input clkin; input datain; output dataout;
always @ (posedge clkin) dataout
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