Synthesis with Icarus Verilog

I really like the idea of using Icarus Verilog as a Synthesis tool in our FPGA flow. I have only used it with a few small test cases.

What's the largest most complex design that you have successfully synthesized using Icarus? How much of a headache was it getting the design through synthesis? How steep is the learning curve if you are accustomed to other synthesis tools?

Thanks, Chris

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