Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15254 Threads Posts
to

Worth reading in Field-Programmable Gate Arrays

locking hdl to a particular fpga

Does anyone know if there is a way to lock code to work only on a particular fpga? I know the device has a jtag identif...
3 comments posted 20yrs
posted by maplante
3 comments posted 20yrs posted by maplante

another FPGA/asic vendor dead :(

NEWS: LeopardLogic has ceased operations. It wasnt directly FPGA but rather asic with part of it as configurable fpga f...
11 comments posted 20yrs
posted by antti
11 comments posted 20yrs posted by antti

Coregen Memory Initialization issue

Hi, I am using Coregen (update 3) from within ISE (7.1 update 4). I added a new source from IP, and defined a RAM. This...
3 comments posted 20yrs
posted by robertsolanki
3 comments posted 20yrs posted by robertsolanki

Single Event Upset

I read about SEU characteristics of Xilinx FPGA. I'm interested in comparation of MTBF data between Spartan3, Virtex-II...
1 comments posted 20yrs
posted by r2d2srbija
1 comments posted 20yrs posted by r2d2srbija

ASIC HDL coding styles

Hello, ALL! Recently I got an example of code, demonstrating some techniques, I also need to implement in my design. Th...
4 comments posted 20yrs
posted by v_mirgorodsky
4 comments posted 20yrs posted by v_mirgorodsky

HDL coding styles

Hello, ALL! Recently I got an example of code, demonstrating some techniques, I also need to implement in my design. Th...
0 comments posted 20yrs
posted by v_mirgorodsky
0 comments posted 20yrs posted by v_mirgorodsky

Cost to go from FPGA to ASIC

How much does it cost to produce an ASIC? This is for a simple customized 8-bit CPU and 64KB of on-chip RAM. If it is a...
19 comments posted 20yrs
posted by bob3635x
19 comments posted 20yrs posted by bob3635x

Anyone know hwicap?

Hello, I'm just starting doing partial reconfiguration through HWICAP on xc2v4000 and confused about its coding. First...
0 comments posted 20yrs
posted by robin.ljw
0 comments posted 20yrs posted by robin.ljw

Xi ISE 7.1 ModelSim

Arg! What did they do to the Waveform and Simulator tools?
0 comments posted 20yrs
posted by bradsmallridge
0 comments posted 20yrs posted by bradsmallridge

Optimizing a State Machine

I designed a SM which can run at 30Mhz below my targe frequency(that's what XST shows after synthesis (no PAR) It is a...
7 comments posted 20yrs
posted by geokirilov
7 comments posted 20yrs posted by geokirilov

crc on only data or including the address

Hello everyone, I am trying to transfer data between on board ethernet PHY and the PC. For that i am implementing ether...
8 comments posted 20yrs
posted by achiluka
8 comments posted 20yrs posted by achiluka

state machine with 2 clock's

is there possobility to use 2 clock's in the same state machine an how thank'
7 comments posted 20yrs
posted by dimon1977
7 comments posted 20yrs posted by dimon1977

Condition Coverage Using ModelSim

When I use a function that returns a boolean in a 'If' condition, ModelSim reports that "Condition Coverage ignoring thi...
0 comments posted 20yrs
posted by aravinth.nathan
0 comments posted 20yrs posted by aravinth.nathan

SDRAM in EDK

Hello! I instantiated SDRAM memory in an EDK project, but I don't know what I have to do in order to boot from it. I wa...
4 comments posted 20yrs
posted by mvetromille
4 comments posted 20yrs posted by mvetromille