Hello, ALL!
Recently I got an example of code, demonstrating some techniques, I also need to implement in my design. The code has been developed in Verilog and was intended to be used as a part of ASIC design. Here is the couple lines from it:
============================================================= // psceq0 :: Prescale Counter Equal to Zero assign psceq0 = ( psc == 5'h0 );
// gpsc[4:0] :: Go clock prescale counter assign gpsc = { 5 { psceq0 & p_clk == 3'h7 } } & 5'hd | { 5 { psceq0 & p_clk == 3'h6 } } & 5'h9 | { 5 { psceq0 & p_clk == 3'h5 } } & 5'h6 | { 5 {~psceq0 } } & psc[4:0] - 5'h1;
// psc[4:0] :: Management clock prescale counter always @ (posedge wclk or posedge rst) begin if ( rst ) psc[4:0]