I designed a SM which can run at 30Mhz below my targe frequency(that's what XST shows after synthesis (no PAR)
It is a pretty big SM(a lot of states, input, output and interna
signals) and I have to optimize it somehow. My question is wha influences the timing so I can concentrate on it I have a Mealy type SM - 2 processes
1st - synch to CLK. the internal signals and outputs are assigne her 2nd - sensitive to all inputs, internel signals(from 1st process) an current state I am using one-hot encoding for the SM ideas ;)