Field-Programmable Gate Arrays

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cic filter

hello all! :P who can tell me how to realize cic decimate filter by FPGA best regard
3 comments posted 20yrs
posted by zhl_gs1980
3 comments posted 20yrs posted by zhl_gs1980

newbie question

Hi all, I am trying to get into FPGA development, just wonder besides "FPGAs are fun" (http://www.fpga4fun.com/WhatAreF...
3 comments posted 20yrs
posted by ppirrip
3 comments posted 20yrs posted by ppirrip

7.1i on Linux installation saga

Thirty hour and several hundred dollars later, it's working great. Details in my blog entry: http://whats.all.this.brouh...
2 comments posted 20yrs
posted by eric
2 comments posted 20yrs posted by eric

ETHERNET MAC

Hello Everyone, I am doing a project on Implementing 10/100 ethernet mac on a fpga using vhdl. I saw the link on fpga4f...
3 comments posted 20yrs
posted by achiluka
3 comments posted 20yrs posted by achiluka

EDK custom IP read/write

Hi, I'm missing something here, I think. I used EDK create/import IP wizard to create a custom IP that has one s/w acce...
1 comments posted 20yrs
posted by dasani8888
1 comments posted 20yrs posted by dasani8888

Xilinx FIFO Generator: FIFO Length

Hi all, I need a 16 words deep FIFO. I'm using the Xilinx FIFO Generator Core. I chosen an asynchronous FIFO, but I fou...
9 comments posted 20yrs
posted by nemesis2001
9 comments posted 20yrs posted by nemesis2001

xpower : logic power=0

dear all I am trying to measuring power consumpsion with VCD and NCD information, in Xpower 6.3.03i, Appication version...
3 comments posted 20yrs
posted by pasacco
3 comments posted 20yrs posted by pasacco

OSD implementation in FPGA

Hi, we have a "Video Monitor On-Screen Display" device from Motorola Semiconductors. (MC141581P2) The problem is that t...
6 comments posted 20yrs
posted by ALuPin
6 comments posted 20yrs posted by ALuPin

System ACE equivalent for CPLDs

I know this isn't exactly comp.arch.cpld... does anyone know of a COTS solution for programming a (Xilinx) CPLD without...
13 comments posted 20yrs
posted by benjamin.toddREMOVEALLCAPITALS
13 comments posted 20yrs posted by benjamin.toddREMOVEALLCAPITALS

Xilinx ISERDES

How many ISERDES are there in an FX12?
11 comments posted 20yrs
posted by bradsmallridge
11 comments posted 20yrs posted by bradsmallridge

Xilinx ML403 Many warnings

Hello, I thought I would load this ML403 board with a program that turns an LED on, which I did, but on the way I encou...
3 comments posted 20yrs
posted by bradsmallridge
3 comments posted 20yrs posted by bradsmallridge

a few questions

Hello, I am experienced with Electronics and programming but never had anything to do with FPGA. I want to start with a...
21 comments posted 20yrs
posted by g.baars13
21 comments posted 20yrs posted by g.baars13

verilog code

Hi, I am new in VLSI field. I have written one verilog code to calulate evenparity of two input data. EX: input data1 i...
3 comments posted 20yrs
posted by hirenshah.05
3 comments posted 20yrs posted by hirenshah.05

XC3S4000 pricing?

Can anyone give me a general idea on pricing and availability for low volumes (~50) of the XC3S4000-5FG900? The only on...
1 comments posted 20yrs
posted by dg2036
1 comments posted 20yrs posted by dg2036