hi, I have a small query in VHDL language. Like we write in Verilog fifo_data
hex rep. in VHDL
Oct 28, 2005
11 Replies
fifo_data
anupam schrieb:
AFAIK this works only if the bus width is a integer multiple of four.
Regards Falk
Anupam, X"AA4F" should work, which simulator do you use? I believe this is a VHDL-93 feature and it is amazing that even in 2005 end (almost 13 years!!) some tools require a Mode-93 kind of switch to their compilers.
Your compiler may need a -V93 or some thing similar.
HTH Ajeetha
formatting link
I always use this(fifo_data
Yes, it does, which is *really* annoying!!!
Why they dont allow something like... foo(4 downto 0)
A dog barking all night or an IRS audit is *really* annoying.
I can tolerate foo(4 downto 0)
Warning #1034: X"1F" width 8 truncated to width 5 in assignment.
Regards, Mark
Here's the deal: The hex notation X"1F" etc was a hack introduced in VHDL-93 to answer users' concerns that they wanted a simple way to write hex literals of vector type.
The "right" way to do it, of course, is...
... use ieee.numeric_std.all; ... signal vec: std_logic_vector(4 downto 0); ... vec
Yes. Your example has a width mismatch. Those above do not. Try it and see.
-- Mike Treseler
Not quite sure what point you're making here Mike?!?
Anyway, to kill the thread, let's agree to disagree. I come from a software background, which might explain why I'm lazy and spoilt with feature-rich languages and powerful pre-processors. ;)
Regards, Mark
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