ASIC HDL coding styles

Hello, ALL!

Recently I got an example of code, demonstrating some techniques, I also need to implement in my design. The code has been developed in Verilog and was intended to be used as a part of ASIC design. Here is the couple lines from it:

============================================================= // psceq0 :: Prescale Counter Equal to Zero assign psceq0 = ( psc == 5'h0 );

// gpsc[4:0] :: Go clock prescale counter assign gpsc = { 5 { psceq0 & p_clk == 3'h7 } } & 5'hd | { 5 { psceq0 & p_clk == 3'h6 } } & 5'h9 | { 5 { psceq0 & p_clk == 3'h5 } } & 5'h6 | { 5 {~psceq0 } } & psc[4:0] - 5'h1;

// psc[4:0] :: Management clock prescale counter always @ (posedge wclk or posedge rst) begin if ( rst ) psc[4:0]

Vladimir -

The coding style probably makes it hard for the synthesizer to perform reasonable optimization of the logic. For example, it may not be able to realize that you're creating a counter. A cleaner coding style would make it more readable for humans as well as for synthesis tools. For example: // psceq0 :: Prescale Counter Equal to Zero assign psceq0 = ( psc == 5'h0 );

always @ (posedge wclk or posedge rst) begin if ( rst ) psc[4:0]

I was always told not to use complicated C-style coding techniques. Simpler styles generally results into better designs. Atleast, this is what my instructor used to say. And he's one of the best in this field!

- Robert.

Hello,

Thanks for all your answers.

So, as I understand, there is no any specific idea bihind this coding style for ASICs. That is good to know.

purposes of verification, testing or whatever else.

With best regards,

- Vladimir