I read about SEU characteristics of Xilinx FPGA. I'm interested in comparation of MTBF data between Spartan3, Virtex-II and especially XC2C and XPLA3 PLDs and commercial sRAM of small capacity (max 512kBy). Do you know something about this issue?
If I didn't worry about SEU in my recent embedded designs with XPLA3, should I worry now when I want to use Spartan3?
Regards, Nebojsa
Nebojsa,
Configuration memory:
Virtex II
40.8 FIT/Mb Spartan 3 39.5 FIT/MbXC2C, XPLA3 CPLDs are tested by our areospace/defense business unit, and you would have to contact them. I do not have their data. They do not use FIT rates, they use cross section. The FIT rate is so low for these devices, when combined with the number of memory cells, the per chip soft fail rate is almost none. It only is of concern in high altitude aircraft, or space applications where the neutron flux is as much as 200 times larger.
1 FIT is defined as one failure per one billion hours. Multiply the FIT/Mb by the Mb of memory in the device to get the soft fail rate for the device itself.Commercial SRAMs are somewhere from 1200 FIT Mb to 6,000 FIT/Mb at the
90 nm technology node.There are some newer devices that are claiming better (see Cypress, for example).
An ASIC SRAM block from a standard library is 5,000 FIT/Mb from a well know foundry.
As for "should I worry", please read:
or
For a 3S50, as an example, take 39.5 * .37 Mb = 14.6 FIT, or 7,818 years mean time between soft failures.
There are ways to mitigate the soft errors, and reduce the FIT rate to nearly 0 by design. Contact your Xilinx FAE for more information.
Austin
PS: for those sharp eyed readers out there, you may notice that the most recent FIT/Mb numbers are slightly higher than ones you may have seen before. Recent work with the standard committee on JEDEC89 (v.4) has led to a number of changes in estimating neutron flux, which we have endorsed by XIlinx, as it makes our data that we have been taking since August 5, 2002, match more closely to all accepted theories and practices.
Nebojsa wrote:
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