Field-Programmable Gate Arrays

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Spartan3 DFS & DLL Behaviour

Using the DFS to multiply a clock leaves some questions for me: The data specifies cycle-to-cycle jitter & period jitte...
0 comments posted 20yrs
posted by filter002
0 comments posted 20yrs posted by filter002

ISE 8.1, EDK 8.1 any pre-release info available?

Hi as the ISE 8.1 is expected this months and EDK 8.1 in December I wonder if some pre release info is already availabl...
4 comments posted 20yrs
posted by antti
4 comments posted 20yrs posted by antti

Xilinx ML403 Virtex 4 IIC uses bitbang test?

I was playing with the Xilinx ML403 Virtex 4 board, and the PowerPC demonstration has a licensed IIC hardware evaluatio...
1 comments posted 20yrs
posted by newman5382
1 comments posted 20yrs posted by newman5382

Semi-OT: LVDS and Cold Sparing

Hi, Don't happen to have an LVDS specification (EIA-644) handy and couldn't find a freebie on the www. So hopefully som...
2 comments posted 20yrs
posted by stellare
2 comments posted 20yrs posted by stellare

Spartan-3E starter kit

Any body knows when the Spartan-3E starter kit will be availaible from Xilinx? Website says 4th quarter. Isn't it 4th qu...
37 comments posted 20yrs
posted by pratipm
37 comments posted 20yrs posted by pratipm

How to reduse the logic.

Hi, 1. I have to get 48 bit output from one of my synthesizable block,So I declared it as output [47:0]Command; reg [47...
2 comments posted 20yrs
posted by himassk
2 comments posted 20yrs posted by himassk

xilinx design reuse netlist format

I have a Verilog module that has been synthesized but not mapped. I would like to be able to reuse the NGC file in anot...
3 comments posted 20yrs
posted by sjjmacls
3 comments posted 20yrs posted by sjjmacls

Xilinx Microblaze prefill icache

Is there a way to: 1. Prefill the Microblaze instruction cache with program 2. Startup with caches enabled and locked T...
1 comments posted 20yrs
posted by alan
1 comments posted 20yrs posted by alan

Virtex-4: SLICEM and SLICEL, why? (Peter Alfke?)

Hello, now Virtex-4 contains the two different slices, SLICEM and SLICEL, like Spartan-3,too. Same reasons? Thanks and g...
3 comments posted 20yrs
posted by WeikEngOff
3 comments posted 20yrs posted by WeikEngOff

Reed Solomon generation / verification

I am looking for a program / a website / or anything that would allow me to verify Reed Solomon code that my FPGA genera...
1 comments posted 20yrs
posted by atarynka
1 comments posted 20yrs posted by atarynka

Virtex-4 DSP48 - special features (Peter Alfke?)

Hello, in the "XtremeDSP for Virtex-4 FPGAs User Guide", on Page 56 are in Table 1-13 some interesting functions mentio...
2 comments posted 20yrs
posted by WeikEngOff
2 comments posted 20yrs posted by WeikEngOff

ethernet phy- DP83847

Hello Everyone, I have few questions regarding the DP83847 PHY. I have this PHY on xilinx virtex fpga board. The data s...
1 comments posted 20yrs
posted by achiluka
1 comments posted 20yrs posted by achiluka

Mitrion-C

I'm wondering if anyone here has ever used Mitrion-C to implement algorithms on FPGAS? If so, what kind of performance h...
3 comments posted 20yrs
posted by robin.bruce
3 comments posted 20yrs posted by robin.bruce

Sigma-Delta A/D

Hallo, is there anybody who can help me to find out the scheme of a 16-bit delta-sigma adc? I have already made some se...
20 comments posted 20yrs
posted by marcotoschi
20 comments posted 20yrs posted by marcotoschi

hex rep. in VHDL

hi, I have a small query in VHDL language. Like we write in Verilog fifo_data
11 comments posted 20yrs
posted by meanupam
11 comments posted 20yrs posted by meanupam