Xilinx ML403 Virtex 4 IIC uses bitbang test?

I was playing with the Xilinx ML403 Virtex 4 board, and the PowerPC demonstration has a licensed IIC hardware evaluation core to communicate with an IIC EEPROM. OK, that sounds reasonable. There are also numerous demo programs that show off the board and Virtex 4 capabilities, which sounds reasonable. Further investigation shows that the iic_eeprom demo program bypasses the IIC core in the demo design via muxes buried in some misc logic in the design, and bitbangs data out to the eeprom via gpio, which does not make much sense to me. Anybody got a clue as to why this was done?


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"Newman" schrieb im Newsbeitrag news: snipped-for-privacy@f14g2000cwb.googlegroups.com...

haha, Xilinx is bypassing its own license?

well as of 'easy' it is actually usually easier and simpler to implement i2c and SPI protocols as bit-bang rahter then learn to the interface to some dedicated hardware.

I usually always implement the bit-bang version first as temporary/test solution. And as we all know the most permanent are things we did develop as temporary solutions. So if the 'temporary' solution was used its very likely to stay permanent.

I think I also have the IIC EDK core license, but I still use the bit bang mostly.


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Antti Lukats

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