I was playing with the Xilinx ML403 Virtex 4 board, and the PowerPC demonstration has a licensed IIC hardware evaluation core to communicate with an IIC EEPROM. OK, that sounds reasonable. There are also numerous demo programs that show off the board and Virtex 4 capabilities, which sounds reasonable. Further investigation shows that the iic_eeprom demo program bypasses the IIC core in the demo design via muxes buried in some misc logic in the design, and bitbangs data out to the eeprom via gpio, which does not make much sense to me. Anybody got a clue as to why this was done?