Using the DFS to multiply a clock leaves some questions for me:
The data specifies cycle-to-cycle jitter & period jitter at the input.
A period jitter of +-1 ns seems not plausible to me. From what ideal clock edge is the +-1ns specified ? From the clock specified in the clocking wizard ? Is the clock frequency specified there getting into the device configuration ? For a 50ns period input +1ns is +2%. This isn't plausible to me as timing of the device changes more than 2% with temperature and supply voltage.
The question is rather:
How would the DFS track a changing input frequency (and device temperature variations and device supply voltage variations of course)? Is there a limit on the speed of this change, before the DFS "unlocks" ?
+-1ns per input clock period ?
For Example a input clock
25ns period, switching to 24ns period in one cycle
A "traditional" PLL with Phase comparator, loop filter & vco has a loop bandwidth, determining the speed of tracking. So it's behaviour would be some kind of step response of the output frequency.
How would the DFS behave ? Can the DFS be used to multiply a clock coming from a variable source ? What's the tracking speed (loop bandwidth)?
Raymund Hofmann