Virtex-4: SLICEM and SLICEL, why? (Peter Alfke?)

Yes, same reason. The LUT-RAM / SRL16 functionality is not really "free", and we think that at least half of the LUTs do not use it. So we saved some area, and you save some money, by deleting this functionality from 50% of the LUTs. It's a typical cost/benefit trade-of... Peter Alfke, Xilinx Applications.

Udo,I am still working on your question about the DSL slices.

Hello Peter,

many thanks for your fast answer and greetings from Germany. I have forgotten one question - Virtex-4 doesn't have internal tristate buffers anymore. Why?

Udo

Tristate buffers on metal lines slow them down and are being phased out of Xilinx devices. If you do need multiple drivers on a single line use a mux instead, they are much faster. I found 2 good threads on the same topic

Thread 1

Thread 2

Kunal