How to reduse the logic.

Hi,

  1. I have to get 48 bit output from one of my synthesizable block,So I declared it as output [47:0]Command;

reg [47:0]Command; and the synthesis report of this block is

Selected Device : 3s50vq100-5

Number of Slices: 51 out of 768 6% Number of Slice Flip Flops: 4 out of 1536 0% Number of 4 input LUTs: 89 out of 1536 5% Number of bonded IOBs: 70 out of 63 111% Number of GCLKs: 1 out of 8 12%

  1. So I used one temperory internal register and assigned to the output, still I got the same result:

output [47:0]Command;

wire [47:0]Command;

reg [47:0]Temp;

assign Command = Temp;

Selected Device : 3s50vq100-5

Number of Slices: 51 out of 768 6% Number of Slice Flip Flops: 4 out of 1536 0% Number of 4 input LUTs: 89 out of 1536 5% Number of bonded IOBs: 70 out of 63 111% Number of GCLKs: 1 out of 8 12%

  1. Then I removed the output and used only the internal register, then I got the good result:

reg [47:0]Command;

Selected Device : 3s50vq100-5

Number of Slices: 4 out of 768 0% Number of Slice Flip Flops: 4 out of 1536 0% Number of 4 input LUTs: 8 out of 1536 0% Number of bonded IOBs: 22 out of 63 34% Number of GCLKs: 1 out of 8 12%

If use Command as only internal register then the logic is less and its utilizing less LUTs. If I make it as output then there is more logic and more LUTs utilization.But I need to get the Command as 48 bit output with less LUTs utilization. Is there any other approach to get Command as output with less logic.

Please suggest me.

Best Regards, HimaSSK.

Reply to
himassk
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My 2 cents: The first two cases are identical. The only difference is that you are naming the nets coming out of the registers in the second case. So no difference in terms of logic resources used. In the third case, the implementation tools have simply optimized away the logic since you didnt use them. Tha can be only the only explaination in the reduction from 51 LUTs to 4!

Reply to
Kunal

Hi, Kunal said it right before. The first two cases are identical. The third has no outputs, therefore optimizes away the register. Mow, if you want 48 Outputs and (just a guess) 22 other I/Os +1 Clock have a look at the used IOBs:

In the first two cases there are 70 IOBs used. (Too much for that small chip anyway) In the third case 48 outputs,are gone leaving 22 used I/Os. This fits into your chip, but all the output registers and their associated logic are gone.

so first of all you need a chip with more pins so the design fits. The number of LUTs is quite irrelevant in this case, because you are using only 5% of the chipsize for logic. And for the observed "reduction" in LUTS: 81 remuved LUTS divided by 48 controlled FFs gives less than two LUTs per FF. This is a quite good ratio.

My recommendation: Read the FPGAs datasheet and understand the SLICE and IOB structure and how the ressources are used by your synthesizer. Understand how to read a synthesis report.

have a nice synthesis

Eilert

himassk schrieb:

Reply to
backhus

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