Sigma-Delta A/D

Very Good!!!

Many Thanks Marco

Now I'm trying to implement the sigma delta a/d. The range of my analog input will be from 0 to 3.3V

Here the scheme of delta sigma modulator:

_______ ________ __________ Analog In --|diff.amp.|---|Integrator|---|Comparator|----> dig.filter --| | | | |with gnd | | | | | ________ | ---------| 1-bit dac|------------------------- | |

It's not clear the function of 1-bit DAC. If it's only 1 bit it should be as a switch, so, in my case, a comparator connected to ground. And also diff.amp should be a comparator?

I think I'm making a mistake.

Could you explain where is wrong?

Many Thanks Marco

Marco skrev:

your scheme is hard to read, you probably used tabs instead of spaces. the DAC should output 0v and 3.3V, your comparator should have a 3.3/2=

1.65V reference

-Lasse

To answer another of Marco's questions, the diff. amp should not be a comparator. It must have a linear output and will usually be based on an op. amp.

Regards, John

Is it possible to use 2 LVDS pins?

Marco

An.In --|diff.amp.|--|Integrator|--|Comparator|-+- dig.filt +-| | | | |with gnd | | | | | ________ | ------------| 1-bit dac|------------------- | |

Sorry, I hope this would be more clear

You could see a clear picture at the following link:

The integrator can be made with a 1-bit accumulator?

And differential amplifier can be made using a IBUFDS?

Many Thanks Marco

Marco schrieb:

Look for US Patents 6,351,145 and 6,246,258 at

They are about implementing ADCs by using differential FPGA inputs as analog comparators.

Kolja Sulimma

Marco, I am afraid not. While the input circuit is differential, the rest of a LVDS buffer is optimised for digital performance, and not for the characteristics we require in a good operational amplifier. A LVDS buffer would make a worse integrator than the cheapest op. amp. so why bother?

Regards, John

Hi John, sorry for my terrible scheme.

Please watch the picture at the link:

That should be more clear.

I thought that I could replace the 1-bit dac using a LVCMOS25 out pin (without dac because it is only 1 bit) and connecting it to the negative input of LVDS25.

What do you think about it?

Is it possible?

Many Thanks Marco

You need to do some simple maths:

16 bits on 3.3V, is a LSB of ~50uV, so if you want to achieve 16 bit ADC performance, your system must be able to resolve to 16 bits.

In operation, think of a SD-ADC as simply a charge balancing system, that makes a heap of Go-Up / Go-Down decisions ( one every clock) and then totals (average) those over a great many clocks.

It relies on the integrator being good enough, that it really does charge balance.

-jg

Jim Granville skrev:

Assuming the threshhold for LVCMOS inputs are close to Vcco/2 with little hysteresis and LVCMOS outputs are close to 0-Vcco outputs. I wonder how well something like this would work?

| FPGA R R | /| Vin >--/\/\/--+--/\/\/--|-| |-- | | \| | | | | |\ +---------|-| |-- | | |/ === | |C _|_

If the Vcco for the bank is from a seperate source, how well will it be isolated from the rest?

-Lasse

That will work, but nowhere near 16 bits - this is good for in the region of 5-8 bits. [We have used this for Low res designs ]

Problems are Vth is part of the Eqn, and the simple RC lacks the long term memory of a true integrator, so you find that linearity at the extreme ends is quite poor. ie it is not true charge-balancing

-jg

Marco, Unfortunately, the DAC output voltage needs to be very well defined and noise-free, even though it is derived from a one-bit value, and no digital output is able to achieve this.

I don't think there is any chance of realising CD-quality (16-bit) audio by trying to make a digital chip perform any analog functions at all. Digital noise on the ground and supply lines for example make it a hopeless job at the quality level you want.

If it is essential to use a single chip, you could investigate the Lattice Semiconductor programmable combined analog/digital chips.

Regards, John

I understand... so a way to do it could be buying a analog devices ad7400 (isolated sigma delta modulator (1 bit out)) and building the digital filter into the fpga to obtain 16 bit output data.

What do you think about it?

I think you should ring up Analog Devices, TI, AKM or Cirrus and buy a $2 ADC that'll kick the ass out of anything you can bodge up in your FPGA. An I2S interface is about six lines of VHDL.

-a

That works just fine, and it can be done in a small FPGA with careful design. I did an 8 channel one in an XC2S15 using external DS modulators.

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Ray Andraka skrev:

I wonder what the intended application is for the ad7400, why the isolation, why only the DS modulator wouldn't most people get a whole ADC when they have to add a chip anyway?

Why did you use it instead of a full ADC, Ray?

-Lasse