Field-Programmable Gate Arrays

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XST vs Synplify

Hi all, I wish to have an idea about how many people here uses Synlify or Leonardo and how many people uses XST. The pu...
3 comments posted 20yrs
posted by francesco_poderico
3 comments posted 20yrs posted by francesco_poderico

FPGA and metastability once again

Hello ALL, I have a design with two global clocks. I have data I need to transfer from one clock domain to another. I a...
5 comments posted 20yrs
posted by v_mirgorodsky
5 comments posted 20yrs posted by v_mirgorodsky

Question on 2048 point FFT( Basic)

Hello FFT guru's I am implementing 2048 point FFT on Virtex as a part of my small project at uni. i want to put couple...
1 comments posted 20yrs
posted by aj.bohra
1 comments posted 20yrs posted by aj.bohra

Microblaze and custom peripherals

Hi, I am wondering if it is possible to implement adding peripheral(s) to the local memory bus of the Microblaze so as...
6 comments posted 20yrs
posted by ssirowy
6 comments posted 20yrs posted by ssirowy

Access to long lines in Virtex-II

Hi, can someone tell me where I can access (read/write) the horizontal long lines in the Virtex-II architecture. In the...
1 comments posted 20yrs
posted by heiko
1 comments posted 20yrs posted by heiko

Aurora over Rocket IO and EDk

Hi , Has anyone implemented a design using Aurora over Rocket IO in EDK...If so please point me to the correct document...
2 comments posted 20yrs
posted by beeraka
2 comments posted 20yrs posted by beeraka

data encryption standard

hi, I am implementing data encryption standard using verilog. can anyone suggest efficient algorith to implemnt data enc...
3 comments posted 20yrs
posted by hirenshah.05
3 comments posted 20yrs posted by hirenshah.05

Stupid reset question

Hello, I'm in the final phase of a design in VHDL on a Cyclon, and i am really puzzled by something. I do not have an e...
12 comments posted 20yrs
posted by nick
12 comments posted 20yrs posted by nick

Disabling Xilinx clock enable usage...

I'm working on a high speed design in a Xilinx V2Pro and I'm running into a timing problem. Instead of packing logic in...
11 comments posted 20yrs
posted by johnp3+nospam
11 comments posted 20yrs posted by johnp3+nospam

Xst optimizes almost everything away

Hi, this is my first real VHDL project, so it's perhaps more a beginner's question than a problem with Xst. I have some...
10 comments posted 20yrs
posted by adi
10 comments posted 20yrs posted by adi

Patient Monitors: Reading RS232 output w/ an FPGA

We currently use a software application (called DataCaptor) to read the MIB-RS232 output of a patient monitor (the Phil...
5 comments posted 20yrs
posted by markebden
5 comments posted 20yrs posted by markebden

Newbie: Problems with clocks

Hello, I just got a new FPGA board (from Avnet, Xilinx Virtex4). The problem is that I never programmend a FPGA before....
4 comments posted 20yrs
posted by Neyer
4 comments posted 20yrs posted by Neyer

Quartus Problem

I have changed from Quartus II 4.2 to 5.1. Now I am getting much more warnings ;-). My design works normally but the wa...
4 comments posted 20yrs
posted by manfred.balik
4 comments posted 20yrs posted by manfred.balik