Simulating PLB DDR in EDK 7.1 SP2 using ModelSim 6.0a

Sure you can simulate that. Do you have the DDR memory simulation models? If not, Micron provides good models on their web site for the individual chips. Other than that, a specific question of what it is you are having trouble with would help; your question is too vague to me (or maybe I am overlooking something).

Thanks for the pointers. I'm trying to observe how my design interacts with the PLB DDR Controller in simulation, but to do so, there needs to be a DDR model with which the PLB DDR Controller can interface in simulation. My design has a master PLB interface that issues writes and reads to the PLB DDR controller. Previously, I have been using a PLB BRAM controller, which I verified works in both simulation and in hardware. However, I have been observing differences when I replace the PLB BRAM controller with the DDR. Specifically, for certain test cases, the design using the DDR controller doesn't work. Since my design interacts with the PLB bus, I did not change it when I switched over from the BRAM controller to the DDR controller.