Field-Programmable Gate Arrays

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Quartus Problem

I have changed from Quartus II 4.2 to 5.1. Now I am getting much more warnings ;-). My design works normally but the wa...
4 comments posted 20yrs
posted by manfred.balik
4 comments posted 20yrs posted by manfred.balik

Uart core for a virtex-4

Hi, I've been using the uart_tx and uart_rx core EDIF's provided by Xilinx in xapp223. These are great for my Virtex-II...
4 comments posted 20yrs
posted by xyz.interactive
4 comments posted 20yrs posted by xyz.interactive

architecture

Hi, I'm intersting to know which architecture is used to create an IP cores : adder/substracter 6.0 ...Thanks.
4 comments posted 20yrs
posted by mazouz.nezhate
4 comments posted 20yrs posted by mazouz.nezhate

JTAG read from xc18v04

Hello, I have a question about reading data from an xc18v04 configuration memory. I am trying clock out 4096 bits plus...
0 comments posted 20yrs
posted by james.knoll
0 comments posted 20yrs posted by james.knoll

XST options in XPS

I am using XPS to synthesize a Microblaze system with custom hardware functions connected with the FSL bus. The synthes...
1 comments posted 20yrs
posted by brassaro
1 comments posted 20yrs posted by brassaro

Reconfiguration Issue -- Pulse Program?

NOTE: This is more of a curiosity than an actual problem. This weekend I discovered some strange behavior after reconfi...
0 comments posted 20yrs
posted by scraven
0 comments posted 20yrs posted by scraven

Modelsim Verification : Retain FSM state names

I would like to monitor the functionality of a state machine I have designed using ISE 7.1. Is there a way to retain th...
6 comments posted 20yrs
posted by me00569
6 comments posted 20yrs posted by me00569

FFT on an FPGA

Q: I'm making a FFT block in hardware (on an FPGA) and I need some advice on multipliers: 1. I have made a simple (Fixe...
3 comments posted 20yrs
posted by satpreetsingh
3 comments posted 20yrs posted by satpreetsingh

using generated timing constraints

Can someone point me to a refernce on how to use the generated time specs generated by the Xilinx Translate progman. Ex...
1 comments posted 20yrs
posted by bgshea
1 comments posted 20yrs posted by bgshea

CLK input DOES NOT use clk pin ( Altera Stratix II)

Hi All! I have a project that use Altera Stratix II 2S180 as ASIC prototype. Because the ASIC has too many interface th...
12 comments posted 20yrs
posted by huangjielg
12 comments posted 20yrs posted by huangjielg

Asynchronous design

Hi, I am designing a peripheral interface IO chip which is also the Intel i82C55 chip. THe problem I have is I want to...
6 comments posted 20yrs
posted by cvdagli
6 comments posted 20yrs posted by cvdagli

input in spartan kit(its urgent)

hi, I made a programe for block matching motion estimation.In this i hav to compare the (4*4) matrics of current frame,...
0 comments posted 20yrs
posted by ravindra28d
0 comments posted 20yrs posted by ravindra28d