Latest threads in Field-Programmable Gate Arrays

How do I find the datasheet of this device "TIOPA 690 3BZL9"?

It has three rows of text printed on the back, and they are "TIOPA 690 3BZL9". I have this chip, but it was fixed to my...

6 20yrs

Francis.invalid

6 20yrs Francis.invalid

Uart core for a virtex-4

Hi, I've been using the uart_tx and uart_rx core EDIF's provided by Xilinx in xapp223. These are great for my Virtex-II...

4 20yrs

xyz.interactive

4 20yrs xyz.interactive

architecture

Hi, I'm intersting to know which architecture is used to create an IP cores : adder/substracter 6.0 ...Thanks.

4 20yrs

mazouz.nezhate

4 20yrs mazouz.nezhate

JTAG read from xc18v04

Hello, I have a question about reading data from an xc18v04 configuration memory. I am trying clock out 4096 bits plus...

0 20yrs

james.knoll

0 20yrs james.knoll

XST options in XPS

I am using XPS to synthesize a Microblaze system with custom hardware functions connected with the FSL bus. The synthes...

1 20yrs

brassaro

1 20yrs brassaro

Reconfiguration Issue -- Pulse Program?

NOTE: This is more of a curiosity than an actual problem. This weekend I discovered some strange behavior after reconfi...

0 20yrs

scraven

0 20yrs scraven

Sounds or other means to indicate end of compilation in Xilinx ISE

I find it frustrating that there is no way or telling if a compilation has ended or not. I can't find any feature in IS...

7 20yrs

fred

7 20yrs fred

Modelsim Verification : Retain FSM state names

I would like to monitor the functionality of a state machine I have designed using ISE 7.1. Is there a way to retain th...

6 20yrs

me00569

6 20yrs me00569

FFT on an FPGA

Q: I'm making a FFT block in hardware (on an FPGA) and I need some advice on multipliers: 1. I have made a simple (Fixe...

3 20yrs

satpreetsingh

3 20yrs satpreetsingh

using generated timing constraints

Can someone point me to a refernce on how to use the generated time specs generated by the Xilinx Translate progman. Ex...

1 20yrs

bgshea

1 20yrs bgshea

CLK input DOES NOT use clk pin ( Altera Stratix II)

Hi All! I have a project that use Altera Stratix II 2S180 as ASIC prototype. Because the ASIC has too many interface th...

12 20yrs

huangjielg

12 20yrs huangjielg

Asynchronous design

Hi, I am designing a peripheral interface IO chip which is also the Intel i82C55 chip. THe problem I have is I want to...

6 20yrs

cvdagli

6 20yrs cvdagli

Assertion file update problem in ModeSim (via Tcl script)

Hi guys, I experience some problem with modeling some designs in ModelSim 5.7 XE 2/Starter trough Tcl script. I have a...

0 20yrs

al.lopich

0 20yrs al.lopich

input in spartan kit(its urgent)

hi, I made a programe for block matching motion estimation.In this i hav to compare the (4*4) matrics of current frame,...

0 20yrs

ravindra28d

0 20yrs ravindra28d

Functional problems with Stratix II when configuring at higher temperatures?

Hello, in my project I have 20 boards with an Altera Stratix II EP2S60 FPGA. When configuring and operating at room tem...

0 20yrs

henn2005

0 20yrs henn2005

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