Hi, I am dealing with reconfigurable computing and relocating modules within a Virtex-II FPGA. In order to save and restore the current flip-flop states I need to determine where to find the states in a readback stream. All necessary equations were provided in xapp151, but only for the Virtex not the Virtex-II FPGAs. Given the row and column, as well as the slice and FF, I would like to know the frame and the offset within the frame where to find the flip flop state. Is there anyone who can help. Regards Heiko
Flip-flop state extraction out of reaback stream in Virtex-II/Pro
Nov 23, 2005
3 Replies
The "-l" option to bitgen will give you an ASCII Logic Allocation file, that gives you these sort of details.
Maybe try the partial-config mailing list. Lots of expertise there. Be warned - partial reconfiguration is a cruel mistress!
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Cheers,
John
Hi John, thanks for you advice. Actually, I knew the -l option and I worked with that for months, but I could not remember that the frame address and offset is in there as well. Do you also have an idea in which frame at which offset to put the a new value for each flip flop, so that after downloading the manipulated bitstream to the FPGA and asserting reset, you have restored a previous state. I will try to mail to the other mailing list as well. Heiko
Are there any equations, how to calculate the frame address and the frame offset out of the X, Y etc. position of the flip-flops or do I have to re-engineer them out of the ll file? Heiko
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