Question on 2048 point FFT( Basic)

Hello FFT guru's

I am implementing 2048 point FFT on Virtex as a part of my small project at uni. i want to put couple of questions.. please help me to your best as i am a starter...:)

I have gone through couple of IEEE papers and i have found that i should use (Mixed Radix alg).i.e. like Radix4 and Radix2 butterflies to implement this algorithm. i have an understanding to use total of 6 stages...i.e. 5 stages of Radix-4 and 1 stage of Radix-2 operations.

Question 1. Is the aforementioned technique the best in terms of speed and area that operation will acquire.?

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Question 2. I am very much confused about the Which ARCHITECTURE that i should use...??(any web links would be great) ?? what would be the input to 2048 point fft... ??l know it has to be streaming data.. where will that input come from....my understanding says that i have to feed x(n) n=0....2047 with data... but its kind of confusing me ... i am checking this site for reference...

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Quetion 3.----> my tutor also asked me to start my project with mapping "one kernel element of FFT to virtex-II board"...So what is the kernel element of FFT ?? .---->is this the Twiddle factor(e to the power of (-j*n*k*2*pi/N)) that is multiplied with the inputs...

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Question 4....----> (Most important for me)----------------> can i know the exact steps that i should follow to implement 2048 point FFT on Virtex2 pro.this answere will solve all my problems.... Ans--------->

Question 5....Can any one tell me any website for getting source code for FFT in VHDL(for my reference) because i am using windows machine and the code from opencores(cf_fft) can be downloaded as .tz format...which i am not able to untar... and it is in verilog as well...

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aj schrieb:

Ans----> That depends. Do you need the speed? What is the required number of Transforms per second? What is your Clock frequency? If you are not going for maximum speed you can save a lot of area by implementing just a single stage and some RAM and a controller that puts the data sequentially through that single butterfly stage. That will cost several clocks to run through the full transformation but you save a LOT of area consuming multipliers.

Answer----> again That depends :-) You should know where you want to connect your FFT-core to. If you know how the Data Is feeded from your data source and you know how you are going to store this data...go ahead and design the interface.

Ans-------> Well, I guess he means one butterfly stage. If you have one of these running you can decide wether you age going to implement something massive parallel or something sequential as mentioned above.

Ans---------> Yes you can! RTFM :-)

Answer -----> Bad excuse.. Use UltimateZIP for instance. Or install cygwin. :-) Also the cf_fft will not be really useful for you because it's originally written in Confluence which outputs verilog code (maybe vhdl as well if you are using the confluence compiler) which I expect hard to read, sice it is machine generated stuff.

Better have a look here :

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It's the first result when you are googeling for: FFT VHDL

Now get busy! :-)

have a nice synthesis Eilert