XST vs Synplify

Hi all, I wish to have an idea about how many people here uses Synlify or Leonardo and how many people uses XST. The purpose of that is undesrtand how many people here beleave that XST is a mature product and it can be trusted or not. At moment I'm tryng to use XST for a small FPGA (spartan 2E 150) and I'm having a lot of trouble. (I have several years of experience and I made design very complex)

For example the xapp807 has source file in VHDL and in Verilog. when I use the verilog version it works fine, but when I use the VHDL version it is unrelaible.

Hope to have feedback from you. Francesco

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Hi Francesco,

I've recently used XST without problems on a Spartan-II with 99% logic utilisation. That's using VHDL. Max. clock speed was 100Mhz. So XST gets my vote.


francesco snipped-for-privacy@yahoo.com wrote:

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Two years ago I tried the same exercise. I took another group's code, enough VHDL to fill an XC2V3000, which would compile under Synplify, and tried to port it to XST. I won't go into details, but I finally had to give up the effort. I suspect part of the problem may have been that the original code was _very_ strict about using unconstrained arrays in _any_and_every_ place it was possible to do so. This means a lot of work for the tool (not to mention the writer).

Here is a link to a very fair, and not too old, article on 'free' tools, like XST, vs. expensive tools like Synplify:

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Quoting from that: "First (at this stage anyway), the commercial EDA tools seem to have an edge in the robustness and versatility in their language front-end. If you don't write perfect, mainstream-style HDL, a commercial tool will often do a better job making some sense of your code and yielding reasonable results than the current crop of vendor-proprietary tools."

Personally, I code to XST, on the assumption that if it makes it there, it'll play anywhere.

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Thanks all, JustJohn XST has been improved a lot from the version 6.1 to 7.1.

2 years ago you tryed XST 5.1 maybe or 6.1..... I found XST (ISE 7.1) much improved but I'm not 100% happy.

Alan thanks for your answer is very important to me.

Thanks again all, Francesco PS: I hope to have some feedback from Xilinx about that :-)

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