Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15254 Threads Posts
to

Worth reading in Field-Programmable Gate Arrays

subtractor

Hi, if I synthese the followng code (substract using two's-complement and adder) using xst and then have a look to the...
9 comments posted 20yrs
posted by olaf
9 comments posted 20yrs posted by olaf

Convert Enumeration to Integer

Hi, I've read the VHDL FAQ 4.2.21 "How to Convert Between Enumeration and Integer Values". Anyway, I have questions to...
0 comments posted 20yrs
posted by olaf
0 comments posted 20yrs posted by olaf

Mobile Chips

I need some information on the type of chips (FGPA, ASICetc) that sits on a mobile phone. We have to implement an algor...
1 comments posted 20yrs
posted by rohit.tripathy
1 comments posted 20yrs posted by rohit.tripathy

PLB GEMAC

Hi, I'm trying to use PLB GEMAC in EDK 7.1, but I don't manage to make standalone application test (provided in EDK) wo...
0 comments posted 20yrs
posted by solazzimarco
0 comments posted 20yrs posted by solazzimarco

How to tell which synthesis tool I am using

Hello, I am have a verilog project which runs on both an altera board, a xilinx board and the (excellent) Icarus simula...
0 comments posted 20yrs
posted by mark.andrew
0 comments posted 20yrs posted by mark.andrew

EDK from ISE

How do I create an embedded subsystem from the ISE? I have done it from EDK and exported it to ISE and Back again it wo...
0 comments posted 20yrs
posted by raybakk
0 comments posted 20yrs posted by raybakk

Partial Reconfiguration Problems

Hello, I'm currently working on a partial reconfiguration project, but I've got some problems during the active and ass...
1 comments posted 20yrs
posted by kramer
1 comments posted 20yrs posted by kramer

Configuration PROM XC18V02 bit error

Anyone experienced a bit error in a configuration PROM? Our design contains a XC18V02 that configures a XCV300 in maste...
2 comments posted 20yrs
posted by larthe
2 comments posted 20yrs posted by larthe

Black Box Attribute in Quartus II

Hi All, I am working on a design targeted to Altera Stratix Gx I am using high speed macro (gxb macro) in the design. w...
3 comments posted 20yrs
posted by kedarpapte
3 comments posted 20yrs posted by kedarpapte

MapLib error for EDK application

I've made a PowerPC Application for Virtex-II FPGA in EDK. The version is 7.1. To generate a bit file using Xilinx ISE,...
0 comments posted 20yrs
posted by milindt
0 comments posted 20yrs posted by milindt

Speed of programming for xc18v04?

My settings are Dell Precision 420, 1GB RAM, Multilinx with COM1, a JTAG chain comprising five xc18v04, one xc18v02. My...
2 comments posted 20yrs
posted by asdf
2 comments posted 20yrs posted by asdf

XST :division and mod in vhdl

Hi, I realize that using XST division and mod is only possible when the divisor is power of 2. May I know whether is th...
7 comments posted 20yrs
posted by novaelf
7 comments posted 20yrs posted by novaelf

FPGA ARM IP Core

Hi Group, from "Actel is bringing ARM7 to the masses with no upfront licensing fees and no royalties" - this is totally...
3 comments posted 20yrs
posted by antti
3 comments posted 20yrs posted by antti