My settings are Dell Precision 420, 1GB RAM, Multilinx with COM1, a JTAG chain comprising five xc18v04, one xc18v02. My FPGA is virtex 2 - 6M gate. It took me some 20 minutes to program each one of the PROM device, and it tend to fail in the middle, maybe 3,4,5th device. Is this normal behavior?
Thanks in advance.
One more question,
My FPGA is tied with the 6 PROMs, so on power on, FPGA is automatically programmed by the PROM. Now some of my PROMs are erased and some failed programming, thus an incomplete bitstream in the PROMs. What will happen when I switch on power? My board gave me dimmly lit LEDs (tied to FPGA pins). Why when I reprogram the FPGA alone via JTAG cable, it always fails?
Previously some other people programmed PROM successfully, FPGA is programmed by PROM upon power-on, and I could reprogram FPGA via JTAG connectors.
Frank
20 minutes a prom is unusually slow. Without timing it on a board I would say 2 minutes should be more like it for each prom.This behaviour is not normal. I would check how the signals look as you are starting to get a sizeable JTAG chain. I would also check if the output TDO lines of each prom need a pullup resistor and the value if fitted. Some parts do need an external resistor and some don't. I think Virtex-2 devices themselves do need an external pullup.
John Adair Enterpoint Ltd. - Soon to be home of Broaddown4. The Ultimate Virtex-4 Development Board.
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