Black Box Attribute in Quartus II

Hi All,

I am working on a design targeted to Altera Stratix Gx I am using high speed macro (gxb macro) in the design.

while doing implementation I want to elaborate the hierarchy by using "Maintain Hierarchy" option in Synthesis. but I don't want to elaborate "gxb macro" part how do I do it...? can I declare that instance as black box...? how to do that in Quartus II...?

Thanks Regards Kedar

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Hi Kedar,

If you are using Quartus Integrated Synthesis, there is no need (or ability in the tool) to black box the altgxb megafunction, since Quartus has the complete implementation available to it.

If you are using Synplify or Precision Synthesis, then you can and should black box this megafunction, and Quartus will fill in the implementation later.

If you are using Quartus Integrated Synthesis and your goal is to make synthesis fast by partitioning up your design so you can synthesize sub-components separately, I'd recommend you use the Quartus incremental compile feature to divide up your design, and then incrementally synthesis (or synthesize & fit) various parts of the design, while other parts are left unchanged. See Chapter 1 of the Quartus handbook at

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for information on how to use incremental compilation.


Vaughn Betz Altera v b e t z (at)

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Vaughn Betz

Hi Vaughn Betz ,

Thank you very much for replying me I got only 1 responce for my Q.. wondering why...?

Any ways actually as you are from Altera corporation I think I can discuss the problem in detail with you...?

First thing is I am stuck with one problem not in Synthesis or Implementation but in Post Implementation simulations. I have already posted my queries on Altera my support but still unsolved.

Let me discuss my problem now.

  1. I am simulating my design using highspeed gxb macros to check actual internal delays of my design. I am using Quartus II 5.0 and Modelsim AE

  1. I am instanciating my design entity more than once in the RTL and I want to check the the interface and glue logic combo delays between the two instances.

  2. My design has a parrallel interface but to check it at high speed I have used gxb SERDES. Similarly in test bench I am using one more gxb component to parallelise the design output and check it.

  1. for this set up when I use a flat netlist and .sdo file the simulation runs fine, but when I use"maintain hierarchy" option for the netlist the siimulation give me wrong library format error for all the stratix GX specific internal components in the net-list. In this case it give an error for "altgxb".

  2. Altera support suggested me to remove SERDES gxb macro instanciated in test bench. this thing works and my purpose got solved of checking internal delays. but the Q remains that by using "maintain hierarchy" option I am changing the design netlist then why I need to remove components from test bench and that removed the library format error...?

Please help me if you can

Regards Kedar

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If possible, you should use the Clear Box flow which will supply the synthesis tool with a good timing model for the megafunction. A simple black box with unknown timing can really confuse timing optimizations.

Ken McElvain

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Ken McElvain

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