Field-Programmable Gate Arrays

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Memory in VHDL

I would like to code the on-chip memory in vendor neutral VHDL. I got it running for a dual-port memory with single clo...
14 comments posted 20yrs
posted by mschoebe
14 comments posted 20yrs posted by mschoebe

case statement fault

Starting from the ISE quick up/down 4bit counter tutorial, I inserted a case statement to handle a single digit 7-segme...
2 comments posted 20yrs
posted by marco
2 comments posted 20yrs posted by marco

Unconnected Ports

When using a xilinx DCM, I receive the following warning - Xst:753 - ... Unconnected output port 'CLK2X' of component '...
4 comments posted 20yrs
posted by weddick
4 comments posted 20yrs posted by weddick

CMOS sensor stops aquring images..

hi, im having a strange problem with the CMOS image sensor ( KAC-9630 ) im using. i've changed the operating mode from...
0 comments posted 20yrs
posted by manusha
0 comments posted 20yrs posted by manusha

What is the definition of steering logic?

Spamming this account signifies your unqualified consent to a free security audit
0 comments posted 20yrs
posted by spammersarevermin
0 comments posted 20yrs posted by spammersarevermin

XC2000

Hello, I would like to ask, if there is any downloadable software to implement designs on XC2000 family devices? I know...
14 comments posted 20yrs
posted by mbr4
14 comments posted 20yrs posted by mbr4

Wishbone comments

After implementing the Wishbone interface for main memory access from JOP I see several issues with the Wishbone specif...
3 comments posted 20yrs
posted by mschoebe
3 comments posted 20yrs posted by mschoebe

Xilinx DCM_ADV 280MHz no lock

Hi, I am trying to generate a serial bit clock for a Camera Link interface and I am having trouble going from 40MHz to...
4 comments posted 20yrs
posted by bradsmallridge
4 comments posted 20yrs posted by bradsmallridge

Bidirectional Bus

H I want to correlate my question to Chintan's problem and Alex answer I usually use the method suggested by Alex to ha...
2 comments posted 20yrs
posted by vera.monaco
2 comments posted 20yrs posted by vera.monaco

virtex II global buffer

H I need to use more than 8 global buffer in a virtex II design I know that VirtexII supports up to 16 Global Buffer di...
1 comments posted 20yrs
posted by vera.monaco
1 comments posted 20yrs posted by vera.monaco

Support for runtime reconfiguration

Hi!, I am a new pg student working on parallelism and FPGA programming. My interest is working at the highest level pos...
0 comments posted 20yrs
posted by c.acosta
0 comments posted 20yrs posted by c.acosta

Design Implementation in Xilinx XST

Greetings everyone, I've recently started working on FPGA designs and was wondering if there is a way to get timing rep...
4 comments posted 20yrs
posted by serith2
4 comments posted 20yrs posted by serith2

Case expression?

For simplicity I would like to do the following CASE (bit1 & bit2 & bit3) IS when "000" => var var END CASE bit1 to 3 a...
13 comments posted 20yrs
posted by fred
13 comments posted 20yrs posted by fred