Latest threads in Field-Programmable Gate Arrays

accessing the phase accumulator in Xilinx DDS 5.0

Hi all, is there a way to access the phase accumulator in Xilinx DDS 5.0? (preferably from VHDL) I'd like to determine...

0 20yrs

dk4xp

0 20yrs dk4xp

simulating code loading in memory and jumping to memory

Hi, I use EDK/ISE/Modelsim. Just want to make some tests and learn on this subject, i would like to create a small syst...

7 20yrs

t

7 20yrs t

Memory in VHDL

I would like to code the on-chip memory in vendor neutral VHDL. I got it running for a dual-port memory with single clo...

14 20yrs

mschoebe

14 20yrs mschoebe

case statement fault

Starting from the ISE quick up/down 4bit counter tutorial, I inserted a case statement to handle a single digit 7-segme...

2 20yrs

marco

2 20yrs marco

Unconnected Ports

When using a xilinx DCM, I receive the following warning - Xst:753 - ... Unconnected output port 'CLK2X' of component '...

4 20yrs

weddick

4 20yrs weddick

CMOS sensor stops aquring images..

hi, im having a strange problem with the CMOS image sensor ( KAC-9630 ) im using. i've changed the operating mode from...

0 20yrs

manusha

0 20yrs manusha

What is the definition of steering logic?

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0 20yrs

spammersarevermin

0 20yrs spammersarevermin

XC2000

Hello, I would like to ask, if there is any downloadable software to implement designs on XC2000 family devices? I know...

14 20yrs

mbr4

14 20yrs mbr4

Wishbone comments

After implementing the Wishbone interface for main memory access from JOP I see several issues with the Wishbone specif...

3 20yrs

mschoebe

3 20yrs mschoebe

Xilinx DCM_ADV 280MHz no lock

Hi, I am trying to generate a serial bit clock for a Camera Link interface and I am having trouble going from 40MHz to...

4 20yrs

bradsmallridge

4 20yrs bradsmallridge

Bidirectional Bus

H I want to correlate my question to Chintan's problem and Alex answer I usually use the method suggested by Alex to ha...

2 20yrs

vera.monaco

2 20yrs vera.monaco

virtex II global buffer

H I need to use more than 8 global buffer in a virtex II design I know that VirtexII supports up to 16 Global Buffer di...

1 20yrs

vera.monaco

1 20yrs vera.monaco

Support for runtime reconfiguration

Hi!, I am a new pg student working on parallelism and FPGA programming. My interest is working at the highest level pos...

0 20yrs

c.acosta

0 20yrs c.acosta

Design Implementation in Xilinx XST

Greetings everyone, I've recently started working on FPGA designs and was wondering if there is a way to get timing rep...

4 20yrs

serith2

4 20yrs serith2

Case expression?

For simplicity I would like to do the following CASE (bit1 & bit2 & bit3) IS when "000" => var var END CASE bit1 to 3 a...

13 20yrs

fred

13 20yrs fred

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