Field-Programmable Gate Arrays

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Question about Progamming File generation report

In my bgn file (report file of the last step: genrate programming file) I got the followig warning: WARNING:PhysDesignR...
2 comments posted 20yrs
posted by taileb.mehdi
2 comments posted 20yrs posted by taileb.mehdi

Xilinx floating point core 1.0

I'm having some hard time to understand what's wrong with this Xilinx floating-point core included in the last IP updat...
8 comments posted 20yrs
posted by "kl31n(get rid of this to write me back)"
8 comments posted 20yrs posted by "kl31n(get rid of this to write me back)"

xilinx constraint

Hello all, Environment details FPGA : Xilinx spartan 3(xc3s200-vq100) speed grade 4 ISE : version 7.1.04i Modelsim : ve...
9 comments posted 20yrs
posted by monica_dsz
9 comments posted 20yrs posted by monica_dsz

mixed signal flash FPGAs launched!

they talked about this producte for more than 3 years ago, now its finally laucnhed * ADC 12bit 600KS/S * MOSFET driver...
4 comments posted 20yrs
posted by antti
4 comments posted 20yrs posted by antti

How can I surpress noise in an ADC board?

While I have only a 40MHz clock connected to a 10 bit ADC, nothing connected to the analog input sockets, the chip is A...
7 comments posted 20yrs
posted by Francis.invalid
7 comments posted 20yrs posted by Francis.invalid

Re: Xilinx FPGA - Wrongly Translated Inputs

>Hello everyone, > >I'm currently using Xilinx ISE 7.1i with the ModelSim XE III/Starter >6.0a simulator. The FPGA whic...
2 comments posted 20yrs
posted by yozara
2 comments posted 20yrs posted by yozara

Which decides my design's max frequency?

Hi, If I have done a circuit design and I want to use it in an acutal environment, I want to my chip to run as fast as...
1 comments posted 20yrs
posted by binary.chen
1 comments posted 20yrs posted by binary.chen

Xilinx for PDP

Dear all, I am new in FPGA field. I am working on designing Logic board for PDP (Plasma display panel). My question is...
0 comments posted 20yrs
posted by bakshi.sandeep
0 comments posted 20yrs posted by bakshi.sandeep

Xilinx FPGA - Wrongly Translated Inputs

Hello everyone, I'm currently using Xilinx ISE 7.1i with the ModelSim XE III/Starter 6.0a simulator. The FPGA which I a...
0 comments posted 20yrs
posted by chloe_music2003
0 comments posted 20yrs posted by chloe_music2003

3/2 with virtex 300

Hi, I use a Virtex XCV300 I would like to do : a multi *3 and a div /2 with a clk = 32 MHz. (I would like to obtain a fr...
11 comments posted 20yrs
posted by bhb22l
11 comments posted 20yrs posted by bhb22l

FPGA in industrial environment

Hi everyone From the point of view of EMI (or any type of interference), are FPGA devices so relyable as ASIC or indust...
4 comments posted 20yrs
posted by calaf_calaf_calaf
4 comments posted 20yrs posted by calaf_calaf_calaf

FreeRTOS.org has support for Microblaze

FreeRTOS.org is an open source mini real time kernel. V3.2.4 is the first version to include a port for the Microblaze....
0 comments posted 20yrs
posted by nospam
0 comments posted 20yrs posted by nospam

modelsim settings in edk

hi, I want to generate simulationlibrarys from edk 6.3 the wizard tells me I have to set the environment variable for mo...
2 comments posted 20yrs
posted by eem
2 comments posted 20yrs posted by eem

Question about Xilinx UCF files

In some reference design (ppc system on Xilinx ML403 board) I found the following contraints in the UCF file: # GPLED 0...
2 comments posted 20yrs
posted by taileb.mehdi
2 comments posted 20yrs posted by taileb.mehdi