Latest threads in Field-Programmable Gate Arrays

fiddling directly with LUT bits on Xilinx

Hi All Is there anyway to directly stash bits into Xilinx (Spartan in this case) LUTs ? I need to hand-build a very smal...

3 20yrs

jdc-rootbeer

3 20yrs jdc-rootbeer

Question about Progamming File generation report

In my bgn file (report file of the last step: genrate programming file) I got the followig warning: WARNING:PhysDesignR...

2 20yrs

taileb.mehdi

2 20yrs taileb.mehdi

Xilinx floating point core 1.0

I'm having some hard time to understand what's wrong with this Xilinx floating-point core included in the last IP updat...

8 20yrs

"kl31n(get rid of this to write me back)"

8 20yrs "kl31n(get rid of this to write me back)"

xilinx constraint

Hello all, Environment details FPGA : Xilinx spartan 3(xc3s200-vq100) speed grade 4 ISE : version 7.1.04i Modelsim : ve...

9 20yrs

monica_dsz

9 20yrs monica_dsz

mixed signal flash FPGAs launched!

they talked about this producte for more than 3 years ago, now its finally laucnhed * ADC 12bit 600KS/S * MOSFET driver...

4 20yrs

antti

4 20yrs antti

How can I surpress noise in an ADC board?

While I have only a 40MHz clock connected to a 10 bit ADC, nothing connected to the analog input sockets, the chip is A...

7 20yrs

Francis.invalid

7 20yrs Francis.invalid

Re: Xilinx FPGA - Wrongly Translated Inputs

>Hello everyone, > >I'm currently using Xilinx ISE 7.1i with the ModelSim XE III/Starter >6.0a simulator. The FPGA whic...

2 20yrs

yozara

2 20yrs yozara

Which decides my design's max frequency?

Hi, If I have done a circuit design and I want to use it in an acutal environment, I want to my chip to run as fast as...

1 20yrs

binary.chen

1 20yrs binary.chen

Xilinx for PDP

Dear all, I am new in FPGA field. I am working on designing Logic board for PDP (Plasma display panel). My question is...

0 20yrs

bakshi.sandeep

0 20yrs bakshi.sandeep

Xilinx FPGA - Wrongly Translated Inputs

Hello everyone, I'm currently using Xilinx ISE 7.1i with the ModelSim XE III/Starter 6.0a simulator. The FPGA which I a...

0 20yrs

chloe_music2003

0 20yrs chloe_music2003

3/2 with virtex 300

Hi, I use a Virtex XCV300 I would like to do : a multi *3 and a div /2 with a clk = 32 MHz. (I would like to obtain a fr...

11 20yrs

bhb22l

11 20yrs bhb22l

FPGA in industrial environment

Hi everyone From the point of view of EMI (or any type of interference), are FPGA devices so relyable as ASIC or indust...

4 20yrs

calaf_calaf_calaf

4 20yrs calaf_calaf_calaf

FreeRTOS.org has support for Microblaze

FreeRTOS.org is an open source mini real time kernel. V3.2.4 is the first version to include a port for the Microblaze....

0 20yrs

nospam

0 20yrs nospam

modelsim settings in edk

hi, I want to generate simulationlibrarys from edk 6.3 the wizard tells me I have to set the environment variable for mo...

2 20yrs

eem

2 20yrs eem

Question about Xilinx UCF files

In some reference design (ppc system on Xilinx ML403 board) I found the following contraints in the UCF file: # GPLED 0...

2 20yrs

taileb.mehdi

2 20yrs taileb.mehdi

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