Hello everyone,
I'm currently using Xilinx ISE 7.1i with the ModelSim XE III/Starter
6.0a simulator. The FPGA which I am downloading my design onto is a Spartan IIE (it's on the Spartan IIE LC Development Kit, with an XC2S300E device).A word of thanks to all those who have helped me in my previous posts before; you've all been a big, BIG help, and I really appreciate it.
I finally found the root of the problem I was having before. The translated verilog model, when simulated, gives me wrong outputs, as compared to the behavioural model. After thorough checking of the simulation results, I realised that all my inputs were wrongly translated and mapped!
My mapped inputs were all in a haywire (e.g. clock has become reset, reset has become cs, sck has become another signal, etc.). Is this the tool's limitation? There were no errors in my design. Neither were there any errors in my Translate, Map or PAR reports. I ran an Assign Package Pins Post-Translate, but I'm not sure if I should make any changes to the LOC-ed input and outpins which I did earlier in Edit Constraints (Text).
Any suggestions as to how I can solve this problem? Please help.
Thanks very much in advance.
Regards, Chloe