In some reference design (ppc system on Xilinx ML403 board) I found the following contraints in the UCF file: # GPLED 0-3 NET gpio LOC = G5; #GPLED0 NET gpio LOC = G6; #GPLED1 NET gpio LOC = A11; #GPLED2 NET gpio LOC = A12; #GPLED3 NET "gpio" PULLDOWN; NET "gpio" TIG; NET "gpio" SLEW = SLOW; NET "gpio" DRIVE = 2;
These I/Os are connected to LEDs. The I/O standard is not mentionned ... I know that for LEDs that doesn't really matter. But by default which standard will be used? The ML403 contains a xc4vfx12-10ff668 FPGA (Virtex-4 FX12)
A+ Mehdi