fiddling directly with LUT bits on Xilinx

You can do this in FPGA Editor. If you are working in Webpack I don't believe that tool is included. You can either tweek the design after p&r or alternative create a macro that you use over and over.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.

"John" schrieb im Newsbeitrag news: snipped-for-privacy@o13g2000cwo.googlegroups.com...

its for virtex but should also work for others

antti

Nice VHDL example. It's pretty simple to do the LUT instantiation in Verilog as well. The INIT parameter just needs the right value which can be provided through localparam values where I0=16'haaaa, I1=16'hcccc, I2=16'hf0f0, and I3=16'hff00. The instantiation is pretty straightforward; one example starts off:

LUT3 #( I0 & I1 | ~I0 & I2 ) MyLut3Name[3:0] ( .O(myOut), .I0( ...