Latest threads in Field-Programmable Gate Arrays

Hello PPl, is there a way of locking a design (NGC) to a particular FPGA board?

We have a very good and expensive design that we want to give freely, as an NGC file, with our generic FPGA products. H...

13 20yrs

jaxato

13 20yrs jaxato

When read back bitstreams from Xilinx PROMs, how to verify?

I am reading back bitstreams from PROMs (5 xc18v04 and 1 xc18v02 in a chain) since I lost the original copy (mixed up w...

0 20yrs

Francis.invalid

0 20yrs Francis.invalid

About Spartan 3

I would like to build an universal measurement device, composed of a frequency meter and a bus protocol analyser (among...

1 20yrs

wyderski

1 20yrs wyderski

MMC(MultiMedia Card) interfacing with FPGA

Hi We are trying to interface a 16MB MMC(of Infineon) to Spartan- FPGA ... We have designed reader for card(in VHDL) ab...

11 20yrs

fahadislam2002

11 20yrs fahadislam2002

Problem with ChipScope Pro 6.2

Hi All, I just got myself an evaluation license for ChipScope Pro 6.2. I used the Core Inserter tool to insert the ICON...

3 20yrs

Sudhir.Singh

3 20yrs Sudhir.Singh

First IP-core designed for and tested with Spartan-3E

The IPcore is very small and actually not S3e only, but it was written because of Spartan3E, namly because S3e added th...

3 20yrs

antti

3 20yrs antti

Xilinx ML40x VGA Documentation

I am looking for further documentation for the VGA connections on the ML40x boards. ug82 says that there is 50MHz chips...

1 20yrs

bradsmallridge

1 20yrs bradsmallridge

Securing verilog source code

Hi, I know tha some EDA tools provide encryption feature to protect confidentiality of the HDL source code but how do w...

2 20yrs

fahad.arif

2 20yrs fahad.arif

Adding "super-LUTs" to FPGA, good idea ?

Hi, A thought cross my mind ... I've been working much on Virtex4 lately and getting fast (~300-350 Mhz) logic for the...

17 20yrs

com.246tNt

17 20yrs com.246tNt

XC4VFX12 -- availability?

I just made the mistake of spending a month designing a board for the Virtex-4 FX without first checking availability....

5 20yrs

acetylcholinerd

5 20yrs acetylcholinerd

ISE purchase

I need to buy a license for ISE Foundation to support some VIIPro work I'm doing. Would it make any difference to the p...

10 20yrs

enquiries

10 20yrs enquiries

No, not FIFOs again...

A need an asynch. FIFO for a Spartan 3E-design, without CoreGen. On the Xilinx-web-page I only found XAPP258, which I c...

10 20yrs

aon.912710880

10 20yrs aon.912710880

ISE = Intelligent Synthesis Expectable :-)

Hi folks, I just stumbled over something funny: I usually write FSMs with registered outputs similar to this example: -...

6 20yrs

nix

6 20yrs nix

How do I find the signature of PROM bitstreams?

Is it possible to read back a xilinx PROM bitstream? I need the Date signature so that I can identify it among 5 of othe...

1 20yrs

Francis.invalid

1 20yrs Francis.invalid

FPGA : MAP slice logic into BLOCK RAM

Hi FPGA : Spartan-3, Xilinx ISE :tools ------------------------------------ have wrote a VHDL code to implement shift r...

4 20yrs

pbijoy

4 20yrs pbijoy

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