Hi all,
i am facing a problem with Xilinx DCM in DFS (not in DLL mode, in which you need to provide a feedback clock for phase alignmen). So my DCM is working in without feedback (internal as well as external) mode.
I am trying to generate a 32Mhz clock from a 16Mhz input clock. Most of the time it works fine but sometimes after giving a reset to FPGA or reprogramming the FPGA the DCM is not able to multiply the clock to give a 32Mhz clock and gives the same input 16Mhz clock as the output.
But according to Xilinx DCM datasheet, in DFS mode we should be able to multiply or divide clocks with frequency > 1 Mhz.
So if anyone has faced any such problem or if there is any synthesis attribute which I need to set etc then please guide me.
Thanks in advance Debashish