Virtex2 I/O state in configure phase

Hi It makes me weird. Till now I thought that on all I/O's is highZ while V2 is configured. But it just before starting to work on some I/O's (I've checked only five or six of all of them) there is logic '1'. I don't know what to think about it.

Device: xc2v2000fg676 -4C, Configure: Slave SelectMap by microcontroller.

Do you have an idea, is it normal and why?

best regards Jerzy Gbur

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How do you mean checked, with a scope? Are these pins connected to anything else on the board?

Could be that there's a pull-up somewhere, incluing a weak pull-up within the FPGA.

Dr. Andrew Greensted      Department of Electronics
Bio-Inspired Engineering  University of York, YO10 5DD, UK
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Andrew Greensted

Look at the definition of the HSWAP_EN pin and how you have it strapped in your design.

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In DS031 it says:- "Depending on the system design, several configuration modes are supported, selectable via mode pins. The mode pins M2, M1 and M0 are dedicated pins. An additional pin, HSWAP_EN is used in conjunction with the mode pins to select whether user I/O pins have pull-ups during configuration." Of course, you know this already because you read the datasheet cover to cover before posting! ;-) HTH, Syms.

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Reply to
Peter Alfke

Peter Alfke napisa³(a):

Thanks all of you. It's great pleasure to have answers so soon.

I work on this project whole last year, so belive me, I've read V2 datasheets :) It's almost finished. We have problems with other chip which is partially controlled by V2. And there I use scope on that line where I saw what I wrote in my previos post. So...

  1. It was scope,
  2. I didn't try to check it by resistor pulldown,
  3. HSWAP_EN='1' or NC - must check it on schema at work, but not before next tuesday :(
  4. Checked lines was V2-outputs/others chips inputs - not pulled/up/down externally.
  5. M2='1' M1='1' M0='0'. - Slave SelectMap mode.

As I wrote earlier I'll be at work next tuesday, and I'll try to use your advices. I'll post results on this topic.

Thank you once more. Best Regards

Jerzy Gbur

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Jerzy Gbur

Jerzy, I advise you to check out Xilinx Answer record 18277

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Jerzy, You may wish to check out Xilinx answer record 18277 if HSWAP_EN = '1'. The title of the Answer Record is : Virtex/Spartan I/O - IO outputs might transition during configuration.

Hope this helps, it was news to me when I heard it.

- Newman

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Time is going so fast....

Ok, my fault, It is following reason of V2 behaving, I've checked lines which was pulluped. That's all, false alert. I'm sorry, I've disturbed you.

Kind regards

Jerzy Gbur

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Jerzy Gbur

Newman napisa³(a):

It's new light on my project. Mhm... I look at it closer on next design.

Thank you very much..

Jerzy Gbur

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Jerzy Gbur

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