Latest threads in Field-Programmable Gate Arrays

ModelSim vsim-3601 message

Good day, I am trying to simulate a design for an Spartan3-200, on Webpack 7.1i SP4 with ModelSim XE III/Starter 6.0a....

3 20yrs

jaac

3 20yrs jaac

Virtex 2 configuration problem

I'm looking for some suggestions as to what else to look at to fix this problem: Using a Virtex II xc2v40 and xcf02s pr...

2 20yrs

gja

2 20yrs gja

ISE Timing

Hello. How can I see what the the clock skew is between a set of register? The clock is an output of a DCM. Also, how ca...

3 20yrs

robnstef

3 20yrs robnstef

How can i get the hex file

Now I read a risc8 and a minimips cpu core ,and I want to know how can I get the hex file for simulation.I don't have th...

0 20yrs

bjzhangwn

0 20yrs bjzhangwn

CORDIC for digital downconversion

I started with Ray Andraka's papers, "A Survey of CORDIC algorithms...", and "High Performance DDC for FPGAs". From the...

8 20yrs

bgaughan

8 20yrs bgaughan

Schematic Entry, Xilinx or Altera?

Greetings. I'm looking at doing some basic CPLD designs via Schematic Entry. Who has easier to learn/use schematic entr...

27 20yrs

skierpaul

27 20yrs skierpaul

URGENT: Virtex-II Pro X - Clock correction questions

In my design I use the block sync and the 64B/66B descrambler and bypasses the 64B/66B decoder in the Rx direction of t...

1 20yrs

no.spam

1 20yrs no.spam

VHDL FF Question

Hi All, I am new to VHDL and am attempting to create an object similar to a parallel load register. Each FF loads its i...

2 20yrs

billingworth

2 20yrs billingworth

ISE Evaluation version

Is there anything that would stop the same version of ISE Evaluation being reloaded onto the same PC or another PC once...

2 20yrs

gerald

2 20yrs gerald

DCM spartan 3 variable frequency divider

Hello all, I am monica from germany.I am using xilinx spartan 3 FPGA.I have a peculiar problem with DCM in spartan 3 FP...

11 20yrs

monica_dsz

11 20yrs monica_dsz

Spartan 3 PCI development card

Hi All, Can anyone reccommend a good PCI development board with a spartan 3 and some DDR SDRAM on it? Thanks

0 20yrs

eternal_nan

0 20yrs eternal_nan

Serious Typo in the Xilinx Floating-Point Core Manual?

http://www.xilinx.com/bvdocs/ipcenter/data_sheet/floating_point.pdf With regard to the speed-optimised single-precision...

2 20yrs

robin.bruce

2 20yrs robin.bruce

Remapping from Virtex-II to Virtex-4

Anyone done any "what-if" remapping of Virtex-II designs to Virtex-4? I wanted to do this to see how the new technology...

5 20yrs

larthe

5 20yrs larthe

A problem of the Dynamic Partial Reconfiguration

Hi All: I have project of the Reconfiguration.I saw the paper "A Module-Based Dynamic Partial Reconfiguration" and make...

0 20yrs

u03104

0 20yrs u03104

[ANNOUNCE] MyHDL 0.5 released

Hi all: I'm pleased to announce the release of MyHDL 0.5. MyHDL is an open-source package for using Python as a hardwar...

4 20yrs

jan

4 20yrs jan

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