Clock related questions

Using the internal 50 MHz clock of the Spartan 3 board, my design synthesized to a speed of 200MHz . If I want my design to synthesize using a new clock( say 4 times the clock freq provided by the board(200MHz)), what should I do? I instantiated the BUFG_DFS_SUBM in my design, which does produce a

200MHz clkfx signal, after a time lag of 950ns. Could you tell me what the LOCK signal is? What is it role and how to use it? Now in my design, in place of using the "clk" of the board, if I use the "clkfx" that I just generated, will my design now synthesize to a higher speed? or is there something else I need to do? Also what is the Xilinx Clocking Wizard? When is it used..what purpose? What does the. xaw file do?
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first of all you should place and route the design and then measure the speed, after synthesis you are not taking the routing delay into account

NO it will not.(assuming you are not canging the vhdl code)

try to put some timing constraints to the CLK (int a *.ucf file) and see what you get

to help the customers to configure the DCM (and not only) in a more friendly way


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Aurelian Lazarut

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