Field-Programmable Gate Arrays

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NMEA Decoder/Display

Hi, Has anybody ever designed anything to decode and display GPS NMEA data coming out in ascii form from a UART? Any id...
8 comments posted 20yrs
posted by alastairlynch
8 comments posted 20yrs posted by alastairlynch

handle-c and xilinx

Hello everybody, sorry in advance if my question will sound stupid but basically I am starting a course in embedded sys...
0 comments posted 20yrs
posted by davidelanNOSPAMMM
0 comments posted 20yrs posted by davidelanNOSPAMMM

multi-processor linux on xilinx

Thanks for all the feedback recently on linux on Xilinx. I think I understand it now: PPC linux is faster and technical...
6 comments posted 20yrs
posted by someone
6 comments posted 20yrs posted by someone

Xilinx compxlib error using VCS

HI, I have just installed Xilinx 7.1 SP3 and trying to compile the libraries in a subdirectory under the install PATH i...
0 comments posted 20yrs
posted by michael_laajanen
0 comments posted 20yrs posted by michael_laajanen

advanced vhdl lerning

hi, i've completed a introdutory vhdl book and done several small scale designs using vhdl for FPGA implementations. Ho...
2 comments posted 20yrs
posted by manusha
2 comments posted 20yrs posted by manusha

core generator

hi, im in the process of implementing the open risc 1000 processor. i have the ISE 7.1 webpack, and it does not contain...
3 comments posted 20yrs
posted by manusha
3 comments posted 20yrs posted by manusha

fpga hardware "breakpoint"

Hello, When doing development using microcontrollers/processors, you can often find ICEs and ICDs that allow you to set...
5 comments posted 20yrs
posted by shawnn
5 comments posted 20yrs posted by shawnn

why such fast placement?

I've recently read some articles stating that a realy fast place and route algorithm for fpgas would be a good thing. I...
6 comments posted 20yrs
posted by hennebry
6 comments posted 20yrs posted by hennebry

quartus and VHDL/Verilog libraries

HI, I am very new to Quartus(5.1 Solaris) and looking for simulation libraries for both Verilog and VHDL, vhdl seams to...
1 comments posted 20yrs
posted by michael_laajanen
1 comments posted 20yrs posted by michael_laajanen

Quartus programmer problem

I've used quartus_pgm in a makefile successfully some time (and perhaps some Quartus version) ago, but now I get a stra...
1 comments posted 20yrs
posted by mschoebe
1 comments posted 20yrs posted by mschoebe

question for the EDK users out there...

Hi , I would realy appreciate it if someone could explain the possible usage of a DCR bus (with PPC or MB). Thanks in ad...
7 comments posted 20yrs
posted by me_2003
7 comments posted 20yrs posted by me_2003

[map error] unable to pack a IBUF into the IOB

hi When exercising xapp290.pdf example, I met following error message during MAP stage. -------------------------------...
2 comments posted 20yrs
posted by pasacco
2 comments posted 20yrs posted by pasacco

Xilinx: generic tristates and multiplexers

Hello all, I have a problem with internal tristates in Xilinx Virtex-2. They basically don't exist, although are widely...
3 comments posted 20yrs
posted by kasty.jose
3 comments posted 20yrs posted by kasty.jose