multi-processor linux on xilinx

Thanks for all the feedback recently on linux on Xilinx. I think I understand it now:

PPC linux is faster and technically superior but monte vista has a strangle hold on the source and tools which discourages anybody from using it.

uClinux/microblaze is slower but more open source and easier to get a system up and running with.

Is that about the picture?

Also, I was wondering if anybody has a multi-processor flavor of Linux running on xilinx? Seems like an obvious next step since there are multiple PPC cores in the chips.

Thanks, Clark

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MontaVista does not have a strangle hold on the anymore than RedHat has a strangle hold on x86 Linux. MontaVista developed the OS adapters for the Xilinx peripheral cores and has submitted them to the appropriate open source repositories. They do provide commercial support and extra benefits by working with them. However, everything required is available open source. Earlier this week I yet again compiled Linux from scratch for the Virtex2Pro PowerPC405 from the excellent Howto hosted by UIUC:

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The same is largely true for Microblaze uclinux. It is an open source project and Petalogix

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is available to provide commercial support/services should that be of interest to you.

In terms of performance, the only difference between Linux and uClinux is the former requires a Memory Management Unit (MMU) while the latter does not. For all intents and purposes that doesn't affect performance directly. The lack of memory protection support can in theory make software more difficult to debug but there are tons of products shipping using uClinux so plenty of folks have figured this out.

In contemporary FPGAs, a hard-core processor such as the PowerPC405 will operate at 300MHz whereas a soft-core processor such as Microblaze operates around 100MHz. However, overall application performance is dependent on many factors besides just the processor core operating frequency.

As for multi-processor designs, neither the PowerPC405 nor Microblaze directly supports cache coherency. However, there are many ways to partition a problem so that more than one processor contributes to the application solution. These issues are discussed here periodically.

A final note. The exciting part about processors in FPGAs is that so many design parameters are flexible--both the hardware and software architectures can be adapted to the problem at hand. Many more opportunities but also much more rope to hang yourself with.

Exciting times!



Reply to
Paul Hartke

MontaVista provides some sort of design environment, and paid support.

You can also get a free Linux distribution and design environment from Denx:

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This was what came with an Avnet V2Pro development card that we bought, and it has worked fine for us. It was the 2.4 version of the kernel.

Is there anyone here that has used MontaVista that would care to comment on their experiences?

I spent about an hour on the phone with someone from MontaVista a while back trying to figure out what they are offering. I asked to have someone technical call me. The person that did call could tell me the price of everything, but could not tell me much more than they provided a design environment and paid support by the "incident". She had no idea what qualified as an incident.

I asked if they would be providing Linux drivers for the Xilinx cores in the EDK. She did not know, but said she would call me back with an answer. I never heard from them again. I wrote my own drivers for what I needed, and did not bother trying to call them again.

While there are two PPCs in many of the Xilinx chips, they do not support cache coherency which you really want if you want to run an SMP single image kernel. You could run two independent copies of the kernel.

Reply to
John McCaskill

Not true. Support for Xilinx PowerPC is available in the linuxppc open source repository which is picked up by various distributions. MontaVista Linux is one such distribution.

Bringing up a Linux system is always a complex task. Linux for MicroBlaze and PowerPC are open source.

The PPCs in Virtex-II Pro and Virtex-4 do not support bus snooping to maintain cache coherency. With that you cannot run the two PowerPCs as an SMP system. However, you can run an instance of Linux per PowerPC.

- Peter

Reply to
Peter Ryser

Thanks for the link. I guess I'm more frustrated with Xilinx then I am with monta vista. I was expecting to go to

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and see:

  1. standard PPC architecture
  2. link to toolsuite
  3. link to source
  4. schematics for standard design (fpga + flash + ram + enet phy, etc.)
  5. tutorial on getting a system up and going

You'd think a company interested in selling chips would make the process a lot easier for us newbies. Instead I've bounced around quite a bit frequently running in to the dead end at the monte vista site which has little if any info for non-subscribers. I'm wondering why I'm forced to go through a meet and greet with MV just to get a platform up that I can evaluate my application on. Are they selling timeshares or something!?

The fact that there are vendors selling boards with V4 FX parts that are choosing to run MB/ucLinux instead of use the PPC core that they already paid for gives me pause and should cause Xilinx to shake their head too.

At any rate, I appreciate the feedback.





Reply to

MontaVista offers commercial support and prebuilt toolchain/environment which mean they will help you bring up _your_ custom platform.

But all the sources / toolchain are available for download. As a matter of fact, I saw a patch to add the Virtex4-FX cpu IDs to the's kernel recently.

On the other hand, a _whole_ lot more people work on microblaze than on Virtex4-FX and those who work on Virtex4-FX may prefer to pay for commercial support to get their application up & running faster. Which is probably why you find more on-line doc on uBlaze than Virtex 4 FX. That said, for a experienced kernel developper, one is not harder than the other ...


Reply to
Sylvain Munaut

As other posters have said, V4FX/V2Pro PPC and MicroBlaze both lack cache coherency support. So, it's not really feasible to implement SMP Linux on either architecture.

We've sketched out plans for a MicroBlaze cache snoop unit and protocol, but ultimately you still require some software-intrusive stuff - slow slow slow.

It's also not very scaleable, a 4-way cache snoop architecture would quickly consume logic gates that would be better used doing real work.

SMP is a compromise. It makes sense if you have to optimise an architecture across as many use-cases as possible - ie fixed silicon. In FPGA-land, we should be designing custom architectures to suit each application, and SMP will rarely be the best architecture for any particular problem.

That said, I do have an implementation of dual mb-uclinux kernels running from the same memory. It works fine, you can use either shared memory or FSL or even ethernet to communicate between them. However, it's not SMP.



Reply to
John Williams

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