Field-Programmable Gate Arrays

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DSP

Please Give me outline of doing a project of dsp processor design.
1 comments posted 20yrs
posted by sahi.cse
1 comments posted 20yrs posted by sahi.cse

SMSC 91c111 and LwIP

Hallo, has someone used that controller with LwIP and a Xilinx FPGA? Where I could find some examples? Many Thanks Marco
2 comments posted 20yrs
posted by marc
2 comments posted 20yrs posted by marc

Xilinx Spartan 3 SSO guidelines for CP132 package?

Hi, When I look in the spartan 3 datasheet I can't find any SSO(simultaneously switching ouput) guidelines for the CP13...
1 comments posted 20yrs
posted by andrew.newsgroup
1 comments posted 20yrs posted by andrew.newsgroup

FPGA work - San Diego area

Electrical Engineer Technical Lead FPGA Position: Electrical Engineer Technical Lead (FPGA) Requirements: 10+ years exp...
0 comments posted 20yrs
posted by michael
0 comments posted 20yrs posted by michael

arctangent again

Hi everyone, I am currently using cordic for arctangent in my system. I need at least 12 bits of accuracy. My x,y input...
3 comments posted 20yrs
posted by kal*
3 comments posted 20yrs posted by kal*

EDK -running from external sram

Hi all, Does anyone knows of a complete reference design (preferably xilinx's) describing a MB system that is running f...
1 comments posted 20yrs
posted by me_2003
1 comments posted 20yrs posted by me_2003

JHDL Application

Dear Sir, We want to use JHDL for our Firewall development. Can tell us please, in which format the JHDL generates outp...
0 comments posted 20yrs
posted by varindra_search
0 comments posted 20yrs posted by varindra_search

SDRAM Reading problem

Hi all, I am new to this group and i am facing one problem regardin reading from the sdram. Actually I am accessing sdr...
0 comments posted 20yrs
posted by raju_eee03
0 comments posted 20yrs posted by raju_eee03

Xilinx 8.1.02i map failure

I downloaded the latest Xilinx service pack today and I'm now seeing Map fail for a pre-existing design. Lat week I sta...
2 comments posted 20yrs
posted by johnp3+nospam
2 comments posted 20yrs posted by johnp3+nospam

Is FPGA code called firmware?

Traditionally, firmware was defined as software that resided in ROM. So, my question is, what do you call FPGA code? Is...
86 comments posted 20yrs
posted by cantsay
86 comments posted 20yrs posted by cantsay

Quartus Tcl interface

Hi, I know that you can use a Tcl script to add pin assignments, by using the "cmp add_assignment" command. Is there a s...
1 comments posted 20yrs
posted by ernielin
1 comments posted 20yrs posted by ernielin

PPC LUT inputs/outputs

Hi, I recently started working with the icap port and have incorporated it into my PPC design using xilinx XPS, and hav...
0 comments posted 20yrs
posted by godzillalad
0 comments posted 20yrs posted by godzillalad