Hi, When I look in the spartan 3 datasheet I can't find any SSO(simultaneously switching ouput) guidelines for the CP132 package. The datasheet has it for VQ100, TQ144 and all the FT/FG BGA packages. But nothing for the CP132. Would it be similar to the BGA packages?
Actually I'm not too sure how the xilinx chip scale package construction(and hence pin inductance) is different than a xilinx BGA....?
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provides the following definition: Chip Scale Package, or CSP, based on IPC/JEDEC J-STD-012 definition, is a single-die, direct surface mountable package with an area of no more than 1.2 X the original die area. The acronym 'CSP' used to stand for 'Chip Size Package,' but very few packages are in fact the size of the chip, hence the wider definition released by IPC/JEDEC.
The IPC/JEDEC definition likewise doesn't define how a chip scale package is to be constructed, so any package that meets the surface mountability and dimensional requirements of the definition is a CSP, regardless of structure. For this reason, CSP's come in many forms - flip-chip, non-flip-chip, wire-bonded, ball grid array, leaded, etc